Demodulators – Phase shift keying or quadrature amplitude demodulator
Reexamination Certificate
2001-05-09
2003-07-15
Pascal, Robert (Department: 2817)
Demodulators
Phase shift keying or quadrature amplitude demodulator
C329S316000, C375S235000
Reexamination Certificate
active
06593805
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a demodulation apparatus for use in a digital transmission unit.
BACKGROUND OF THE INVENTION
Conventional demodulation of an input modulated wave in a digital transmission unit is performed in the following way. An analog-to-digital (A/D) converter samples an analog baseband signal at a rate higher than a symbol rate (originally, a transmission rate of digital data), that is, a sampling frequency approximately sixteen times as high as the symbol rate to convert it into a digital signal. To restore the symbol rate, time-positions to be decided are estimated, and the signal is then decimated. The signal further undergoes frequency error estimation, data decision and the others. It should be noted that there are cases where a digital filter, a phase converter or a delay detector is provided at the subsequent stage of the A/D converter.
In the above case, the sampling frequency needs to be kept high for the estimation of the time-positions to be decided, so that a demodulation apparatus needs to be operated at an increased frequency. Consequently, the demodulation apparatus can hardly be implemented in an integrated circuit (IC) utilizing a generalized process or the like.
Moreover, with an increased occupied bandwidth of the signal received or the like, a frequency response and the others of the A/D converter are requested more strictly than ever.
There is one method known as a solution to the above problems. According to this method, an interpolator is provided at the subsequent stage of the A/D converter. Data undergo interpolation after sampling performed by the A/D converter so as to be reproduced through upsampling. The interpolation is done by inserting one data “0” or data “0” to the number of a given number into a string of data that is converted into the digital signal by the A/D converter.
According to the above method, the sampling frequency can be equal to or higher than the Nyquist frequency covering a frequency band of the input signal, thereby alleviating the requests to the A/D converter. However, the interpolation eventually requires a high-rate operation, and the frequency at which the demodulation apparatus is operated cannot thus be reduced. Accordingly, there is no choice but to increase a clock frequency required for oversampling or upsampling, and this circuit is thus hardly implemented in the IC utilizing the generalized process or the like.
SUMMARY OF THE INVENTION
The present invention addresses the problems discussed above and aims to reduce a frequency required for the operation of a demodulation apparatus.
The present invention utilizes redundancy of upsampling, so that a channel filter is comprised of a plurality of parallel transversal filters. With this structure, even though a sampling rate required of an A/D converter is determined in consideration given to the effect of interference or the like that is present in the vicinity of a signal band, a clock frequency required of the transversal filters at the subsequent stage can be equal to a symbol rate, and decision equivalent to an arbitrary oversampling number is feasible. Consequently, the clock frequency of the demodulation apparatus can be reduced, the channel filter having a flat group-delay response can be implemented, and degradation of the demodulation apparatus can be reduced.
REFERENCES:
patent: 4910468 (1990-03-01), Ohtsuka et al.
patent: 5068667 (1991-11-01), Mizoguchi
patent: 5524125 (1996-06-01), Tsujimoto
patent: 05-260108 (1993-10-01), None
patent: 06-260887 (1994-09-01), None
patent: 11-004272 (1999-01-01), None
Kunieda Yoshinori
Tomita Kazuo
Yomo Hidekuni
Glenn Kimberly E
Pascal Robert
RatnerPrestia
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