Demapping system and method

Details Demapping system and method Demapping system and method

2005-10-04

2005-10-04

Liu, Shuwang (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S253000, C375S261000, C714S780000, C714S796000

Reexamination Certificate

active

06952458

ABSTRACT:
A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger cifor each i, the challenger ciis a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mifor each i, the reliability miis the reliability of the hard demapper output d; and calculates soft bit xifor each i, the soft bit xiis calculated based on the reliability mi.

REFERENCES:
patent: 6058146 (2000-05-01), Yoshida
patent: 6195396 (2001-02-01), Fang et al.
patent: 6353911 (2002-03-01), Brink
patent: 6738949 (2004-05-01), Senda et al.
patent: 2002/0114398 (2002-08-01), Lin et al.

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