Delta-sigma modulator for power amplification of audio signals

Details Delta-sigma modulator for power amplification of audio signals Delta-sigma modulator for power amplification of audio signals

2001-08-16

2002-08-20

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C375S247000

Reexamination Certificate

active

06437719

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to delta-sigma (&Dgr;&Sgr;) modulators that are preferable for use in power amplification circuits of audio signals.
2. Description of the Related Art
Conventionally, power amplifier circuits for audio signals are designed to perform power amplification by effecting pulse-width modulation (PWM) at their output stages, which yields a high efficiency in power amplification. In addition, it is possible to provide a delta-sigma modulator at an input stage of the power amplifier circuit for audio signals. Here-in, power amplification is performed such as to realize switching using an output of the delta-sigma modulator.
FIG. 7
shows a simple circuit configuration for use in conventional delta-sigma modulators.
In
FIG. 7
, an analog signal is input to a signal input terminal
110
and is added together with an output of an inverter
62
by an adder
63
. An output of the adder
63
is subjected to integration by an integrator
60
, an integration result of which is forwarded to a clocked comparator
61
. The clocked comparator
61
performs quantization in such a manner that the integration result of the integrator
60
is compared with the reference voltage in synchronization with a clock frequency f
CLK
. That is, the clocked comparator
61
produces a 1-bit digital signal based on the integration result of the integrator
60
by quantization. Such an output of the clocked comparator
61
is delayed by one sample and is then fed back to the adder
63
by way of the inverter
62
. That is, the inverter
62
acts as a feedback delay circuit for the delta-sigma modulator. As described above, the delta-sigma modulator of
FIG. 7
is characterized in that the clocked comparator
61
outputs a series of 1-bit digital signals.
The delta-sigma modulator performs analog-to-digital conversion based on an input analog signal to produce 1-bit digital signals based on comparison results of the clocked comparator
61
, an example of which is shown in FIG.
8
.
FIG. 8
shows a string of pulses having pulse widths that are varied in response to comparison results of the clocked comparator
61
. Therefore, the clocked comparator
61
outputs digital signals in such a discrete manner that their values are adequately altered between logic 0 and logic 1 with reference to a reference pulse width corresponding to the clock frequency f
CLK
. Herein, the clocked comparator
61
uses the ‘fixed’ clock frequency f
CLK
. In order to perform high-precision analog-to-digital conversion, it is necessary to perform so-called ‘over-sampling’ techniques. For this reason, it is necessary to increase the clock frequency to be sufficiently high.
In order that the aforementioned delta-sigma modulator produces digital signals at a sampling frequency fs of 48 kHz, for example, the clock frequency f
CLK
should be greatly increased in proportion to the sampling frequency fs in order to achieve high-precision analog-to-digital conversion. Here-in, the clock frequency f
CLK
should be normally increased to 64 fs or so, that is, 3 MHz.
To operate the delta-sigma modulator at the aforementioned clock frequency f
CLK
, the clocked comparator
61
outputs 1-bit signals at a maximal inverse frequency, which is set at ½ f
CLK
. Herein, the maximal inverse frequency is defined as a maximal value of the inverse number of the period by which an output of the clocked comparator
61
is inverted.
Switching 1-bit signals at a large power may cause various problems. That is, the switching loss becomes large as the maximal inverse frequency becomes high. In that case, the delta-sigma modulator must is subject to the problem of the heating of the switching elements. In addition, it also suffers from other problems due to electromagnetic radiation (or radiation of electromagnetic waves).
Due to the aforementioned problems, it may seem rational to simply perform the power amplification by pulse-width modulation, rather than by using the delta-sigma modulator for the power amplification of audio signals.
However, even if the audio system as a whole is configured to operate based on digital signals only, it is necessary to perform digital-to-analog conversion for power amplification of audio signals at once. In that case, the power amplifier circuit would have to carry out complicated processing for effecting pulse-width modulation.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a delta-sigma modulator that can increase the sampling frequency for analog-to-digital conversion without increasing the inverse frequency for 1-bit digital signals output from a clocked comparator corresponding to a 1-bit quantizer.
According to a first aspect of the invention, a delta-sigma modulator is configured by an integration circuit, a 1-bit quantizer, an output inversion inhibitor circuit, a delay circuit, and an adder. An analog signal is supplied to the integration circuit by way of the adder, wherein it is subjected to integration. An integration result is subjected to quantization by the 1-bit quantizer to produce 1-bit digital signals. The output inversion inhibitor circuit inhibits an output signal of the 1-bit quantizer from being re-inverted during a re-inversion inhibiting period corresponding to a preset number ‘N’ (where N≧2) of clock pulses counted after the timing when the output signal of the 1-bit quantizer is inverted. An output of the output inversion inhibitor circuit is delayed by one sample and is then fed back to the adder by way of the delay circuit.
According to a second aspect of the invention, a delta-sigma modulator is configured by at least a pair of an adder and a switched-capacitor integrator, a 1-bit quantizer, an output inversion inhibitor circuit, and a delay circuit. An analog signal is supplied to the switched-capacitor integrator by way of the adder, wherein it is subjected to integration. An integration result is subjected to quantization by the 1-bit quantizer to produce 1-bit digital signals. The output inversion inhibitor circuit inhibits an output signal of the 1-bit quantizer from being re-inverted during a re-inversion inhibiting period corresponding to a preset number ‘N’ (where N>2) of clock pulses counted after the timing when the output signal of the 1-bit quantizer is inverted. An output of the output inversion inhibitor circuit is delayed by one sample and is then fed back to the adder by way of the delay circuit.
In the above, the preset number ‘N’ is set to five, for example. Hence, the output inversion inhibitor circuit neglects a re-inversion of the output signal of the 1-bit quantizer unless five consecutive clock pulses are completely counted after the timing when the output signal of the 1-bit quantizer is inverted.
Due to the provision of the output inversion inhibitor circuit, it is possible to perform analog-to-digital conversion at the ‘increased’ sampling frequency without increasing the inverse frequency for 1-bit digital signals output from the 1-bit quantizer, which acts as a clocked comparator operating based on clock pulses.


REFERENCES:
patent: 4264974 (1981-04-01), Crouse
patent: 5610606 (1997-03-01), Fukunaga
patent: 5920273 (1999-07-01), Hirano
patent: 5974089 (1999-10-01), Tripathi et al.
patent: 6018262 (2000-01-01), Noro et al.
patent: 6097259 (2000-08-01), Saito

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