Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-11-21
2001-10-09
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S143000, C341S076000, C341S077000, C341S155000, C341S061000, C341S141000
Reexamination Certificate
active
06300890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delta-sigma modulator (here on abbreviated as &Dgr;&Sgr; modulator) that uses a 1-bit quantizer, and also relates to an AD converter for converting an analog signal into an equivalent digital signal. More particularly, the present invention relates to an improvement in &Dgr;&Sgr; modulators and AD converters, which can quantize an input analog signal by means of a feedback loop including a 1-bit quantizer and reduce the quantization noise to the same level as a theory value expected when the quantization is performed using a feedback loop including a multiple-bit quantizer instead of the 1-bit quantizer.
2. Description of the Prior Art
Conventionally, such a &Dgr;&Sgr; modulator is disclosed in Japanese patent application publication (TOKKAIHEI) No. 4-229722 and Japanese patent application publication (TOKKAIHEI) No. 11-308110th. Referring now to
FIG. 6
, there is illustrated a block diagram showing the structure of a conventional &Dgr;&Sgr; modulator as disclosed in the references. In the figure, reference numeral
24
denotes an input terminal, numeral
25
denotes a first-stage subtracter, numeral
26
denotes a first-stage integrator, numeral
27
denotes a final-stage subtracter, numeral
28
denotes a final-stage integrator, numeral
29
denotes a 1-bit quantizer, numeral
30
denotes an output terminal, numeral
31
denotes 1-bit DA converter, and numeral
32
denotes a delay element.
In operation, when an input analog signal is input to the input terminal
24
, the input analog signal is delivered to the 1-bit quantizer
29
through the first-stage subtracter
25
, the first-stage integrator
26
, the final-stage subtracter
27
, and the final-stage integrator
28
. At this time, the first-stage subtracter
25
outputs the input analog signal as it is when nothing has been input to the input terminal
24
before the input analog signal is input, and the final-stage subtracter
27
outputs a first-order integration value of the input analog signal input from the first-stage integrator
26
as it is. Therefore, a second-order integration value of the input analog signal is output from the final-stage integrator
28
. The 1-bit quantizer
29
compares the value of the analog signal applied thereto with a predetermined threshold. The 1-bit quantizer
29
outputs a 1-bit digital value “1” when the value of the analog signal is greater than the threshold. When the value of the analog signal is less than the threshold, the 1-bit quantizer
29
outputs a 1-bit digital value “0”.
When the 1-bit digital value output from the 1-bit quantizer
29
is “1”, the 1-bit DA converter
31
outputs a quantized analog signal at the threshold level. In contrast, when the 1-bit digital value is “0”, the 1-bit DA converter
31
outputs a quantized analog signal without any level. The delay element
32
delays this quantized analog signal by only one sampling time of the 1-bit quantizer
29
. The first-stage subtracter
25
and the final-stage subtracter
27
output values obtained by subtracting the quantized analog signal from respective inputs applied thereto.
In such the &Dgr;&Sgr; modulator, quantization error dependent on the level difference between the threshold level in the 1-bit quantizer
29
and the input analog signal is generated without exception since the 1-bit quantizer
29
quantizes the input analog signal, and outputs the quantized analog signal as a digital signal value.
It is known to be able to decrease the quantization error theoretically by replacing the 1-bit quantizer
29
with a multiple-bit quantizer as shown in FIG.
7
. In
FIG. 7
, reference numeral
33
denotes a multiple-bit quantizer, and numeral
34
denotes a multiple-bit DA converter. However, when replacing the quantizer with a multiple-bit one like this, it is necessary to also replace the 1-bit DA converter
31
with the multiple-bit DA converter
34
. As a result, unit element circuit variations (Em_dac) in the multiple-bit DA converter
34
may result, and therefore the quantization error cannot be reduced to a theory value in actuality.
Referring next to
FIG. 8
, there is illustrated a block diagram showing the structure of another conventional &Dgr;&Sgr; modulator that can reduce the quantization error to the same level as a theory value expected when replacing the quantizer with a multiple-bit one. In the figure, reference numeral
35
denotes a multiple-bit quantizer, numeral
36
denotes a differentiator, numeral
37
denotes a differentiation integrator, and numeral
38
denotes an adder. The multiple-bit quantizer
35
quantizes a quantized analog signal from a 1-bit DA converter
31
, and the differentiator
36
calculates the second derivative of the output of the multiple-bit quantizer
35
. The differentiation integrator
37
performs a predetermined differentiation and integration process on a quantized digital signal from a 1-bit quantizer
29
, and the adder
38
adds the output of the differentiator
36
to the output of the differentiation integrator
37
and outputs a digital signal by way of an output terminal
30
.
Since the prior art &Dgr;&Sgr; modulator employs the 1-bit quantizer
29
for the feedback loop, further quantizes the quantized analog signal by means of the multiple-bit quantizer
35
, and adds this result to the quantized digital signal output from the 1-bit quantizer
29
, the prior art &Dgr;&Sgr; modulator can reduce the quantization noise to the same level as a theory value expected when the quantization is performed using the feedback loop including a multiple-bit quantizer instead of the 1-bit quantizer.
However, it is necessary to add various circuits, such as the differentiation integration circuit
37
, the differentiator
36
, and so on, between the 1-bit quantizer
29
and the adder
38
, and between the multiple-bit quantizer
35
and the adder
38
for this additional processing, and, as a result, there is a problem that the circuit scale increases.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above-mentioned problem. It is therefore an object to provide a &Dgr;&Sgr; modulator and an AD converter capable of quantizing an input analog signal by means of a feedback loop including a 1-bit quantizer and reducing the quantization noise to the same level as a theory value expected when the quantization is performed by using a feedback loop including a multiple-bit quantizer, with fewer circuit scale than prior art &Dgr;&Sgr; modulators.
In accordance with an aspect of the present invention, there is provided a &Dgr;&Sgr; modulator comprising: an input terminal to which an input analog signal is input; an output terminal via which an output digital signal is output; a 1-bit quantizer located between the input terminal and the output terminal, for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal; a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal; a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer; a delay element for delaying the quantized analog signal from the 1-bit DA converter; an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by the delay element from the input analog signal input to the input terminal, and one integrator at a final stage outputting its output to the 1-bit quantizer; a multiple-bit quantizer for quantizing an analog output of the subtracting circuit and for outputting a second quantized digital signal; a differentiator for calculating an Nth-order derivative of the second quantized digital signal from the multiple-bit quantizer, N being equal to a number of the one or more stages included in the input integrating circuit series;
Kumamoto Toshio
Morimoto Yasuo
Okuda Takashi
Burns Doane , Swecker, Mathis LLP
Mai Lam T.
Mitsubishi Denki & Kabushiki Kaisha
Tokar Michael
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