Delta-sigma modulator

Details Delta-sigma modulator Delta-sigma modulator

2002-03-18

2003-02-04

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S118000, C341S120000, C341S144000, C341S155000

Reexamination Certificate

active

06515607

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a delta-sigma modulator. In particular, the present invention relates to a bandpass delta-sigma modulator for reducing multi-bit feedback error.
2. Description of the Related Art
In wireless communication, CMOS ICs are not only applied to digital signals in base frequency, but also in intermediate frequency and radio frequency. Therefore, many kinds of circuits are combined in an IC, which solves the problems of integrating bipolar transistors and CMOS transistors.
Presently, bandpass delta-sigma modulators are applied to converting an intermediate frequency signal from analog to digital. The conventional bandpass delta-sigma modulator comprises two kinds of quantizers. One is a one-bit quantizer to eliminate the characteristic of the offset of the direct current, and the other is a multi-bit quantizer to raise the level of the amplitude of vibration to decrease the quatization error between each level.
The performance of delta-sigma modulators is sensitive to input noise, so one-bit DAC is fed back to its first stage due to its better linearity, and multi-bit DAC is fed back to the other resonators behind the first one for its better signal-to-noise ratio (SNR). That is, the one-bit signal at the output of the circuit is fed back to filter in the first stage to eliminate the error, and the multi-bit signal at the output of the circuit is fed back to filter in the second stage. Therefore, the output of the quantizers comprises one-bit and multi-bit noise shaping signals. Then, the one-bit noise shaping is converted by a digital circuit to eliminate the error and improve the performance of the circuit.
Unfortunately, the multi-bit feedback has its inherent elements mismatched caused by process variation, and these errors can be regarded as a quantized nonlinearly noise, which will affect the accuracy of the delta-sigma modulator.
FIG. 1
shows the linear model of a two-stage bandpass delta-sigma modulator. In
FIG. 1
, x is used as the symbol for an input signal; E
1
and E
2
are used as the symbols for the quatization error of the one-bit quantizer
13
and multi-bit quantizer
14
, respectively. E
3
is used as the symbol for the error of the DAC feedback loop; Y
1
and Y
2
are used as the symbols for the output of the one-bit quantizer
13
and multi-bit quantizer
14
, respectively. In addition, the two bandpass filters (
11
and
12
) are used, the transfer function of the bandpass filters in z-domain are
z
-
1
1
+
z
-
2
.
Therefore, the ideal output of the linear model is
Y=X·z
−2
+E
2
·(1
+z
−2
)
2
  (1)
Because the multi-bit quatization error is less than the one-bit quatization error, the signal-to-noise ratio is strong at the output. However, formula (1) is only an ideal result, in fact, the error E
3
of the DAC feedback is ignored. If the bandpass filter
12
is Y′, than Y′ is
Y′=X·z
−2
+E
1
·z
−2
+(
E
2
+E
3
)
·z
−2
(1
+z
−2
)  (2)
Therefore, the output Y
1
of the one-bit quantizer 13 and the output Y
2
of the multi-bit quantizer 14 are changed as:
Y
1
=Y′+E
1
=X·z
−2
+E
1
·(1
+z
−2
)·z
−2
·(1
+z
−2
)  (3)
Y
2
=Y′+E
2
=X·z
−2
+E
1
·z
−2
+(
E
2
+E
3
)·
z
−2
·(1
+z
−2
)
+E
2
  (4)
Then, the signals Y
1
and Y
2
are input to digital filter 16. At this time, the formula (4) is multiplied by (1+z
−2
), then minus formula (3) multiplied by z
−2
, so the output Y is:
Y=X ·z
−2
+E
2
·(1
+z
−2
)
2
+E
3
·z
−2
·(1
+z
−2
)  (5)
The formula (5) comprises DAC error E
3
, which shows the influence by E
3
upon output Y. In formula (5), E
3
will increase the noise of output Y. Therefore, the noise shaping comprises one level, which will decrease the signal-to-noise ratio.
Therefore, if the levels of the noise shaping of E
3
and E
2
are the same, and the original feedback is kept, the output signal Y will have better performance and signal-to-noise ratio.
According to formula (5), if E
3
is changed to E
3
·(1+z
−2
), the dynamic element selection circuit completes the (1+z
−2
) function on the z-domain. The variable ‘z
−1
’ represents delaying a sample cycle in time-domain, the variable ‘+’ represents repeating selection, and the variable ‘−’ represents not repeating selection.
Hence, to obtain the selection capability of the (1+z
−2
) function, the selected elements must be repeated with the one selected twice backwards, and the element selected twice forwards must be repeated with the selected elements. That is, two adjacent selections only relate to the selections made twice backwards and twice forwards, but there are no rules between them.
The input signals of DAC are separated from odd group and even group, each group is selected back and forth. For example, in
FIG. 2
, if the input sequence of DAC is
3
,
4
,
4
,
3
,
6
,
5
,
5
, and
6
. The odd times input are
3
,
4
,
6
, and
5
, and the even times input are
4
,
3
,
5
, and
6
. The first time the DAC selects three elements from left to right, and the second time the DAC still selects four elements from left to right. At the third time, the DAC selects four elements from the last elements at the selection of the first time to the left. At the fourth time, the DAC selects three capacitors from the last capacitor at the selection of the second time to the left.
Therefore, there are four modes while the DAC is selecting:
(1). In the odd times of the selection, the selection is toward the right.
(2). In the odd times of the selection, the selection is toward the left.
(3). In the even times of the selection, the selection is toward the right.
(4). In the even times of the selection, the selection is toward the left.
The dynamic element selection changes the appearing frequency of the error of the elements by timing selection. For frequency-domain, a zero pole is added in the frequency band to eliminate the errors. For example, the zero pole of the function (1+z
−2
) is at a quarter of the sampling frequency, which is the frequency of the signals.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a delta-sigma modulator, which combines multi-feedback with one-level noise shaping. One dynamic element selection circuit is applied to the multi-bit feedback loop to minimize the DAC mismatch error. After digital circuit processing, the output nonlinearity error of the delta-sigma modulator is suppressed with second-order noise shaping for multi-bit quantized noise and the same order noise shaping for element mismatching one in multi-bit feedback loop.
To achieve the above-mentioned object, the present invention provides a delta-sigma modulator for converting an external analog signal to a digital output signal. The delta-sigma modulator comprises a first filter circuit, a second filter circuit, a one-bit quantization, a multi-bit quantization, a digital-to-analog converter, and a digital filter. The first filter circuit outputs a first analog signal according to the external analog signal and a one-bit output signal. The second filter circuit outputs a third analog signal according to the first analog signal and a second analog signal. The one-bit quantization converts the third analog signal into the one-bit output signal. The multi-bit quantization converts the third analog signal into a multi-bit output signal. The digital-to-analog converter comprises a plurality of capacitors, which determines the number of capacitors to be charged according to the multi-bit output signal, then selects the capacitors to be charged in a predetermined turn and charge the capacitors. When the digital-to-analog converter receives the alternate multi-bit output signal, the digital-to-analog converter

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