Delta-sigma analog-to-digital converter with pipelined...

Details Delta-sigma analog-to-digital converter with pipelined... Delta-sigma analog-to-digital converter with pipelined...

2007-05-29

2008-10-07

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

07432841

ABSTRACT:
A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A second, coupled multi-stage delta-sigma modulator quantizes less significant bits of the input signal, wherein a first quantization stage is coupled to the first quantization error signal to quantize the next most significant bits of the input signal and produce a second quantization error signal. A second quantization stage is coupled to the second quantization error signal to quantize the least significant bits of the input signal and produce a third quantization error signal. A noise-shaping filter is coupled to the third quantization error signal, the output of which is subtracted from the first quantization error signal to produce said input of the first quantization stage.

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Brooks, T. L., et al., “A 16b ΣΔ Pipeline ADC with 2.5MHz Output Data-Rate,” 1997 IEEE International Solid-State Circuits Conference, Feb. 7, 1997, pp. 208-209, 458, IEEE.
Brooks, T. L., et al., “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” IEEE Journal of Solid-State Circuits, Dec. 1997, pp. 1896-1906, vol. 32, No. 12, IEEE.
Staszewski, R. B., et al., “Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Nov. 2003, pp. 815-828, vol. 50, No. 11, IEEE.
Bosi, A., et al., “An 80MHz 4x Oversampled Cascaded ΣΔ-Pipelined ADC with 75dB DR and 87dB SFDR,” IEEE International Solid-State Circuits Conference, 2005, pp. 174-175, 591, IEEE.

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