Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Patent
1996-05-02
1998-10-13
Hoff, Marc S.
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
343155, H03M 302, H03M 112
Patent
active
058218904
ABSTRACT:
A .DELTA..SIGMA. analog-to-digital converter having a built-in variable gain end is disclosed including a .DELTA..SIGMA. analog-to-digital converter portion, the converter portion having an amplifier for amplifying and outputting an input signal, a charging device for accumulating a signal voltage, a plurality of switches coupling the input signal to the charging device and coupling the voltage accumulated in the charging device to the amplifier, and a comparator for producing a HIGH output if the output of the amplifier becomes above a predetermined level, and producing a LOW output if the output of the amplifier becomes below the predetermined level, and an AGC controller both ends of which are coupled to a reference voltage, the controller generating a voltage reduced into 1/N of the reference voltage through switches at respective nodes of a plurality of resistors.
REFERENCES:
patent: 5541599 (1996-07-01), Kasha et al.
patent: 5548833 (1996-08-01), Townsend
patent: 5581213 (1996-12-01), Under et al.
Shih et al.; "A CMOS 5-V Analog Front End for 9600-bits/Facsimile Modems"; IEEE Journal of Solid-State Circuits, Dec. 1987, vol. SC-22, No. 6, pp. 990-995.
Kim et al.; "A Single Chip .DELTA.-.SIGMA. ADC with a Built-In Variable Gain Stage and DAC with a Charge Integrating Subconverter for a 5 V 9600-b/s Modem"; IEEE Journal of Solid-State Circuits, Aug. 1995, vol. 30, No. 8, pp. 940-943.
Kim et al. A Single Chip Sigma delta . . . Charge Integrating Subconverter; IEEE Journal of Solid State Circuits, Aug. 1995, vol. 30, No. 8 pp. 940-943, Aug. 1995.
Jeong Deog Kyoon
Kim Daejong
Hoff Marc S.
Jean-Pierre Peguy
LG Semicon Co. Ltd.
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