Delta-sigma analog-to-digital converter (ADC) having an...

Details Delta-sigma analog-to-digital converter (ADC) having an... Delta-sigma analog-to-digital converter (ADC) having an...

2008-04-29

2008-04-29

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

11534191

ABSTRACT:
A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.

REFERENCES:
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patent: 6738004 (2004-05-01), Melanson
patent: 7145486 (2006-12-01), Chokhawala et al.
patent: 7193549 (2007-03-01), Nanda et al.
patent: 7221302 (2007-05-01), Melanson
U.S. Appl. No. 11/297,016, filed Dec. 8, 2005, Melanson et al.
U.S. Appl. No. 11/297,011, filed Dec. 8, 2005, Melanson.
Robert, et al., “A Second-Order High-Resolution Incremental A/D Converter with Offset and Charge Injection Compensation”, IEEE JSSC, vol. 23, No. 3, Jun. 1988.
Quinquempoix, et al., “A Low-Power 22-bit Incremental ADC with 4ppm INL, 2ppm Gain Error and 2uV DC Offset”, Proceedings of ESSCIRC, Grenoble, FR 2005.
Cirrus 5361 Datasheet, Cirrus Logic Inc,, Feb. 2005.

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