Delta sigma analog-to-digital converter

Details Delta sigma analog-to-digital converter Delta sigma analog-to-digital converter

2001-04-09

2002-10-29

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S157000, C341S166000, C341S167000

Reexamination Certificate

active

06473018

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog-to-digital converter (ADC) for analog voltage-to-digital value conversion and, more particularly, to a delta sigma ADC making utilization of a switched capacitor circuit.
U.S. Pat. No. 6,037,887 discloses a delta sigma ADC having programmable gain. However, this ADC has a bipolar analog input range, or an analog input range (e.g., from −10 V to +10 V) in symmetry with respect to signal ground.
In various determination applications, ADCs having a unipolar analog input range (e.g., from 0 V to +10 V) are required. However, conventional delta sigma ADCs are unable to meet such a requirement and half of the bipolar input range is wasted uselessly.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a delta sigma ADC having a unipolar analog input range.
The present invention provides a delta sigma ADC having an analog input range in asymmetry with respect to a certain bias voltage and the delta sigma ADC of the present invention employs a configuration comprising (a) sampling means for sampling, in synchronization with an input clock signal, an analog input voltage, (b) addition/subtraction means for selectively adding either of a subtraction and addition voltages differing from each other to the sampled voltage, (c) an integrator for integrating a voltage obtained by the selective addition, (d) a comparator for comparing a voltage obtained by the integration with the bias voltage, (e) delay means for delaying the output of the comparator by one clock cycle of the input clock signal, and (f) control means for controlling the selection between the subtraction voltage and the addition voltage in the addition/subtraction means in response to the output of the delay means.


REFERENCES:
patent: 4588981 (1986-05-01), Senn
patent: 5134401 (1992-07-01), McCartney et al.
patent: 5659314 (1997-08-01), Tokura et al.
patent: 5754131 (1998-05-01), Ribner et al.
patent: 6037887 (2000-03-01), Wu et al.
patent: 6064871 (2000-05-01), Leung

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