Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2007-09-13
2008-12-16
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
07466257
ABSTRACT:
The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator. When integration functions used to obtain an n-th order noise-shaping effect are multiplexed and operated using a single integrator, the integrator's current consumption can be suppressed.
REFERENCES:
patent: 5659314 (1997-08-01), Tokura et al.
patent: 5896101 (1999-04-01), Melanson
patent: 6087969 (2000-07-01), Stockstad et al.
patent: 2005-72632 (2005-03-01), None
Koh, et al., “A 66dB DR 1.2V 1.2mW Single-Amplifier Double-Sampling 2nd-order ΔΣ ADC for WCDMA in 90nm CMOS,” ISSCC 2005, Session 9, Switched-Capacitor ΔΣ Modulators, IEEE International Solid-State Circuits Conference.
Adachi Hisashi
Akizuki Taiji
Maeda Tomoaki
McDermott Will & Emery LLP
Panasonic Corporation
Young Brian
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