Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-04-03
2001-08-07
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S156000
Reexamination Certificate
active
06271782
ABSTRACT:
1 FIELD OF INVENTION
The field of invention is data conversion, more particularly, this invention relates to oversampling analog-to-digital converters.
2 DESCRIPTION OF PRIOR ART
Delta-sigma modulation has been used successfully for the implementation of high-resolution A/D converters. The general concept is shown in FIG.
1
. The analog input signal g(k) is converted to a digital representation d(k) using an N-bit delta-sigma modulator [
32
]. The resolution N of d(k) is lower than the A/D converter system's [
30
] effective resolution, but the sampling frequency of d(k) is comparably higher than twice the system's [
30
] bandwidth, i.e., d(k) is an oversampled signal. A signal's sampling frequency divided by twice the system's [
30
] bandwidth is called the signal's oversampling ratio OSR, which is always greater than one. Thus, d(k) is not an accurate representation of g(k) on a sample-to-sample basis, but a good delta-sigma modulator [
32
] will ensure that the spectral composition of g(k) and d(k) are essentially linearly related in the system's [
30
] signal hand. A multi-rate decimation filter [
34
] is generally used to suppress the spectral components of d(k) outside the signal band, and to lower the sampling frequency such that the overall output signal s(k) is only slightly oversampled.
Single-bit delta-sigma modulators [
32
], i.e., modulators for which N=1, have generally been preferred because they can be designed to be inherently linear. However, single-bit modulation requires the oversampling ratio of d(k) to be very high, say 128, if the overall effective resolution is to be in the order of 16 bits. Thus, single-bit delta-sigma modulation has been used mainly for the implementation of audio A/D converters, which are characterized by high demands for linearity in a relatively low bandwidth; approximately 100 dB performance in a 20 kHz bandwidth.
Several new applications, including digital communication systems such as xDSL modems, require high-resolution A/D conversion in a bandwidth of several mega Hertz. Delta-sigma modulation is a very interesting technique also for such applications, simply because the linearity requirements are more strict than what can be fulfilled using other techniques in low-cost integrated-circuits technologies. The relatively high bandwidth implies that d(k) should be oversampled as little as possible because the sampling frequency of the analog delta-sigma modulator [
32
] cannot be increased arbitrarily.
The simplest way to lower the oversampling ratio without degrading the performance is to increase the resolution N of d(k). The bottleneck in the design of multi-bit delta-sigma modulators [
32
] used to be the design of an internally-used feedback D/A converter, which must be very linear. However, with the development of mismatch-shaping D/A converters (see, e.g., U.S. Pat. Nos. 5,138,317; 5,221,926; 5,404,142; and 5,684,482) it has become feasible to implement inherently linear multi-bit delta-sigma modulators [
32
]. The complexity of these mismatch-shaping circuits unfortunately becomes impractically high when the resolution N is significantly higher than (say) 6 bits. Although good wide-bandwidth delta-sigma A/D converters [
30
] can be implemented to operate with an internal resolution of only 6 bits, it is clearly preferable to increase the internal resolution if this can be obtained without significantly increasing the modulator's [
32
] complexity. One important incentive to increase the internal resolution is that the decimation filter [
34
] thereby can be simplified. The decimation filter's [
34
] complexity and power consumption is often comparable to, or even higher than, that of the delta-sigma modulator [
32
]. Thus, simplifications of the decimation filter [
34
] are to be considered important improvements of the system [
30
].
High-Resolution Delta-Sigma Modulators.
U.S. patent application with Ser. No. 60/044,665, filed by the applicant for this patent, describes the most efficient mismatch-shaping D/A converters developed so far. It facilitates 100 dB performance at only 10 times oversampling, and the circuit's complexity is relatively low and essentially independent of the resolution N. Hence, these mismatch-shaping D/A converters are very useful for the implementation of delta-sigma modulators [
32
] operating with a high physical resolution N.
FIG. 2
shows the general topology of a delta-sigma modulator [
32
]. The feedback DAC [
42
] generates an analog feedback signal a(k) which must be a very accurate representation of d(k) in the signal band. An analog adder/subtractor [
44
] calculates the difference c(k) of the input signal g(k) and the analog feedback signal a(k). A linear loop filter [
40
] selectively amplifies e(k) in the signal band. The amplified error signal v(k) is fed to the loop quantizer [
38
] generating d(k), whereby the loop is closed. Assuming stability, the error signal's e(k) spectral power density will be inversely proportional the loop filter's [
40
] gain. Thus, using a high-gain loop filter [
40
] the signal-band power of e(k) can be made negligible, whereby the signal-band equivalence of d(k) and g(k) will be as good as the feedback DAC's [
42
] linearity.
According to the above discussion, it is preferable that the loop quantizer's [
38
] resolution N be as high as possible. However, to preserve stability, the loop quantizer's [
38
] and the feedback DAC's [
42
] combined delay may not exceed one clock cycle. Fast (low-latency) high-resolution quantizer's are generally massive circuits with a high power consumption; the use of them should be avoided, if possible. High-resolution quantizers are most easily implemented as multi-step quantizers, but their throughput (i.e., the maximum sampling frequency) is relatively low unless pipeline techniques are employed. Pipelined quantizers, however, cannot be used to implement the loop quantizer [
38
] because their delay will make the closed-loop delta-sigma modulator [
32
] unstable. It should also be considered that the feedback DAC [
42
] must provide a very linear D/A conversion, i.e., it should preferably be mismatch-shaping. Mismatch-shaping DACs require that some numerical computations be performed, which will further increase the loop delay. The performance of mismatch-shaping DACs can generally be improved if they are allowed some latency (say, two clock cycles).
3 SUMMARY
A delta-sigma modulator according to this invention comprises a pipelined multi-step quantizer quantizing the sum of the input signal g(k) and the loop filter's output signal v(k). Only the multi-step quantizer's last stage is used to quantize the loop filter's output v(k), thus adding only very little to the loop delay. The loop filter is implemented as a multi-path mixed-delay feedback structure allowing the feedback DAC several clock cycles of latency without compromising the modulator's stability.
3.1 Objects and Advantages
Accordingly, several objects and advantages of the invention are
to provide a stable delta-sigma modulator structure in which a pipelined multi-step quantizer is used for the generation of a high-resolution output signal;
to provide a stable delta-sigma modulator structure for which the latency of the critical feedback DAC may be several clock cycles, thus facilitating the use of low-power digital circuitry to implement mismatch-shaping algorithms in high-speed delta-sigma ADCs;
to provide a delta-sigma modulator structure suitable for high-resolution A/D conversion of signals with a bandwidth of several mega Hertz;
to provide a simple delta-sigma modulator structure providing a high-resolution output signal
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