Delivering a fine delay stage for a delay locked loop

Details Delivering a fine delay stage for a delay locked loop Delivering a fine delay stage for a delay locked loop

2001-05-31

2002-10-29

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S233000

Reexamination Certificate

active

06472921

ABSTRACT:

TECHNICAL FIELD
This invention relates to delivering a fine delay stage for a delay locked loop (DLL) that incrementally varies the phase shift of input and output voltages.
BACKGROUND
Double data rate synchronous dynamic random access memory (SDRAM) is available today in new memory integrated circuits that are designed with DLLs. Among their many applications, DLLs perform synchronization in a delay chain having the amount of fixed unit delays changed by a controller which evaluates a phase detector. DLLs have commonly been designed to have a coarse delay stage and fine delay stage where a coarse delay stage is larger than a fine delay stage. Since a coarse delay is process dependent, a coarse delay cannot be made very small to improve the resolution of the DLL, so a fine delay stage is used to improve the resolution.
SUMMARY
The invention relates to a circuit that produces a fine delay stage for a DLL and a corresponding method that incrementally varies the phase shift of input and output voltages to achieve the fine delay stage.
In general, in one aspect, the invention is directed to a fine delay unit circuit, for use in a DLL, that provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch.
This aspect may include one or more of the following features. Each current source may be a constant current source. The plural current sources may include a first current source and a second current source. The second current source may generate twice as much current as the first current source. Each additional current source may generate current 2
N
times greater than the first current source.
Each current source may include a first transistor. Each current source switch may include a first transistor and a second transistor. The second transistor may receive a fourth signal that is complementary to a third signal received by the second transistor. The first input switch may include a first transistor and a second transistor. The second input switch may include a third transistor and fourth transistor. The first transistor may receive the first signal and the second transistor may receive a third signal complementary to the first signal. The third transistor may receive the second signal and the fourth transistor may receive a fourth signal complementary to the second signal.
In general, in another aspect, the invention is directed to a method that provides a phase-shifted output relative to a first signal in a DLL. The method includes selecting varying amounts of current from plural current sources by enabling current source switches, and transmitting a first signal to a first input switch and a second signal, phase-shifted from the first signal, to a second input switch. Using this method, the phase-shifted output relative to the first signal is based on an amount of current that passes through the first input switch and the second input switch.


REFERENCES:
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patent: 4128817 (1978-12-01), Gomi
patent: 5015872 (1991-05-01), Rein
patent: 5489869 (1996-02-01), Mulbrook
patent: 6285228 (2001-09-01), Heyne et al.
patent: 6385265 (2002-05-01), Duffy et al.
patent: 199 9801 (1999-06-01), None
patent: 199 29801 (1999-06-01), None

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