Delayed state writes for an instruction processor

Details Delayed state writes for an instruction processor Delayed state writes for an instruction processor

1997-11-19

1999-05-18

Lall, Parshotam S.

Boots, shoes, and leggings

36471604, 36472604, 36473605, 36474814, G06F9/38

Patent

active

059058811

ABSTRACT:
An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.

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