Delayed negative feedback circuit

Details Delayed negative feedback circuit Delayed negative feedback circuit

1993-02-23

1994-06-28

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 19086

Patent

active

053249976

ABSTRACT:
A modification to the design of high speed logic circuitry will increase the speed of the circuitry. The modification consists of a delayed negative feedback added to the interface between two gates (a driving gate and a driven gate). The feedback is delayed by a time similar to the gate propagation delay, so that when a transition occurs, the feedback is effectively positive for times less than the feedback delay time. The effect of this is to add a bias at the interface that will aid the next transition of the driven gate during the transition. After a transition, the polarity of the bias is reversed so it will again aid the next transition.

REFERENCES:
patent: 4400632 (1983-08-01), Kushner
patent: 4521700 (1985-06-01), Blumberg et al.
patent: 4563600 (1986-01-01), Kobayashi et al.
patent: 4609837 (1986-09-01), Yagyuu et al.
patent: 5233239 (1993-08-01), Sato

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