Delayed FIFO status for serial shift emulation

Details Delayed FIFO status for serial shift emulation Delayed FIFO status for serial shift emulation

1993-06-30

1997-04-08

Teska, Kevin J.

Boots, shoes, and leggings

3642323, 3642385, 364239, 3642396, 364DIG1, G06F 9455, G06F 1300

Patent

active

056196814

ABSTRACT:
Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.

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Microcom Reference Manual, "Parallel Port Operation" p. 27, 1993.

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