Delayed acknowledgement in an asymmetric timer based LAN communi

Details Delayed acknowledgement in an asymmetric timer based LAN communi Delayed acknowledgement in an asymmetric timer based LAN communi

1994-10-25

1996-06-18

Beausoliel, Jr., Robert W.

Excavating

370108, H04J 306, H04L 118

Patent

active

055286054

ABSTRACT:
A computer communications system has a controller for controlling a master with a circuit timer, the circuit timer is capable of aggregating data produced during a circuit timer interval into a single master message, and the data is produced by a plurality of users, where each user is capable of establishing a plurality of sessions. There is a communication pathway, responsive to expiration of the circuit timer interval, for sending the aggregated data to a slave. Also there is a acknowledgement circuit for the slave to send an acknowledge message to the master upon expiration of a delay ACK time interval, the delay ACK time interval is greater than the circuit timer interval, and the circuit timer is capable of initiating sending of a plurality of master messages during one delay ACK time interval. Further, there is a delay acknowledgement circuit, responsive to receipt of the plurality of master messages, for the slave to acknowledge the plurality of master messages in one acknowledge message, and each user and each session being acknowledged by the one acknowledge message.

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