Delay value adjusting method and semiconductor integrated...

Details Delay value adjusting method and semiconductor integrated... Delay value adjusting method and semiconductor integrated...

2007-05-22

2007-05-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

C327S264000, C327S278000

Reexamination Certificate

active

10968944

ABSTRACT:
The method provides wide-range delay value adjustment without making changes in cell size and metal wiring, even when a process variation occurs. Threshold values of some or all of the transistors which form the delay gate inserted into the signal path are varied to control the delay value of the delay gate, so that the delay value of the signal path is adjusted.

REFERENCES:
patent: 5039893 (1991-08-01), Tomisawa
patent: 5227679 (1993-07-01), Woo
patent: 5486774 (1996-01-01), Douseki et al.
patent: 6117735 (2000-09-01), Ueno
patent: 6172545 (2001-01-01), Ishii
patent: 5-226619 (1993-09-01), None
patent: 5-226988 (1993-09-01), None
patent: 5-268015 (1993-10-01), None

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