Delay unit implemented by inverting circuits associated with cap

Details Delay unit implemented by inverting circuits associated with cap Delay unit implemented by inverting circuits associated with cap

1991-08-12

1993-07-20

Sikes, William L.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

3073031, 3073032, 307592, 307594, 307595, 257369, H03K 513, H01L 2500

Patent

active

052296679

ABSTRACT:
A delay unit incorporated in a standard cell type semicustom-made integrated circuit comprises a plurality of complementary inverting circuits coupled in cascade for introducing a time delay into propagation of a signal, and a lead circuit coupled to one of the complementary inverting circuits for increasing the time delay, and the plurality of complementary inverting circuits and the load circuit are formed in and one a plurality of rectangular active areas defined by a thick field oxide film grown on a major surface of a semiconductor substrate, wherein the thick field oxide film penetrates into two of the rectangular active areas so as to form respective bifurcated portions, one of the complementary inverting circuits and the load circuit being formed in the bifurcated portions so that large channel resistance of the complementary inverting circuit and large capacitance of the load circuit are easily produced without changing the arrangement of the rectangular active areas.

REFERENCES:
patent: 3134026 (1964-05-01), Earle
patent: 4045688 (1977-08-01), Stewart
patent: 4477736 (1984-10-01), Onishi
patent: 4482825 (1984-11-01), Nozaki et al.
patent: 4516312 (1985-05-01), Tomita
patent: 4868627 (1989-09-01), Yamada et al.
patent: 5097159 (1992-03-01), Seki et al.
IBM Tech. Discl. Bult. vol. 27 #12 "CMOS Delay Circuit";, May, 1985; p. 7134.

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