Boots – shoes – and leggings
Patent
1994-04-06
1996-06-18
Trans, Vincent N.
Boots, shoes, and leggings
364488, G06F 1750
Patent
active
055285112
ABSTRACT:
A delay time verifier to verify the delay time for a logic circuit using a time verification model prepared according to the graph theory. It comprises a verified model information file to store in advance the delay time verification information for each of the arcs in the time verification model including delay time for each rise/fall type of the signal at the start point node and the end point node of the arc, an invalidness specifier to specify an arc with invalid data and rise or fall of the signal to be invalidated for the arcs where only one of rise and fall signals is allowed to be valid, a modifier to modify the delay time verification information stored in the file so that the information for the arcs whose rise or fall signal specified by the invalidness specifier becomes invalid is modified, and a delay time verifier to verify the delay time of the logic circuit based on the delay time verification information after modification by the modifier.
REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5210700 (1993-05-01), Tom
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5355321 (1994-10-01), Grodstein et al.
patent: 5396435 (1995-03-01), Ginetti
NEC Corporation
Trans Vincent N.
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