Delay time estimation method and recording medium storing...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing

Reexamination Certificate

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C703S013000, C703S014000, C703S015000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

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07127385

ABSTRACT:
The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

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