Delay time checking arrangement

Details Delay time checking arrangement Delay time checking arrangement

1988-12-12

1990-11-20

Atkinson, Charles E.

Excavating

371 62, G01R 3128

Patent

active

049724126

ABSTRACT:
A circuit arrangement for checking excessive time delay in the propagation of signals between two circuit blocks is provided in which two successive square wave clock signals are generated, each having a cycle period equal to the maximum permissible time delay, and a test signal is propagated between the circuit blocks initiated together with the first clock signal. The times of receipt by the second circuit block of the test signal and each clock signal are stored, and means are provided for producing a disparity signal whenever there is a disparity between the two stored signals. A third clock signal is generated which lags the second clock signal and this is compared with the disparity signal to produce an excess delay indicating signal whenever they simultaneously occur.

REFERENCES:
patent: 4058767 (1977-11-01), Muehldorf et al.
patent: 4063080 (1977-12-01), Eichelbarger et al.
patent: 4146835 (1979-03-01), Chnapko et al.
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4736351 (1988-04-01), Oliver
patent: 4876501 (1989-10-01), Ardini et al.

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