Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2001-04-10
2002-12-10
Wong, Don (Department: 2821)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C716S030000
Reexamination Certificate
active
06493660
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a delay time calculating method for use in a hierarchical design, and more specifically to a delay time calculating method for use in a hierarchical design, capable of accurately calculating the relation between the delay amount of a partial chain and the delay amount of a whole chain.
In a circuit design, a delay of a partial buffer chain of chained buffers is calculated. In comparison with the whole of the chained buffers, the partial buffer chain is considered to be a low level layer in a hierarchical design. The delay time calculating method for use in the hierarchical design is known as shown in
FIG. 5
, in which the reference signs T$
01
to T$
13
designate buffers, respectively. In the example shown in
FIG. 5
, a “0”th level layer, that is the whole of the chained buffers T$
01
to T$
13
, is called a top layer or an upper level layer. From the top layer, a partial buffer chain, that is a part of the whole, is cut out as a “Macro A”. This “Macro A” is called a low level layer or a first level layer. The remaining top layer is constituted of a partial chain consisting of the buffers T$
01
to T$
3
, and another partial chain consisting of the buffers T$
11
to T$
13
. The “Macro A” is constituted of still another partial chain consisting of the buffers T$
4
to T$
10
.
In accordance with a prior delay time calculating method for the above mentioned hierarchical structure, the delay of the “Macro A” constituted of the chained buffers T$
4
to T$
10
is calculated, and the obtained delay amount is annotated as a first annotation (Step S
1
) Then, the delay of the top layer constituted of the buffers T$
01
to T$
3
and T$
11
to T$
13
is calculated, and the obtained delay amount is annotated as a second annotation (Step S
2
). Finally, the sum of the first annotation and the second annotation is calculated, so that the delay amount of the whole is obtained.
In this calculation, however, the existence of delay influence factors “Cload” and “Trf” shown in
FIG. 4
is disregarded.
FIG. 4
shows some number of chained (or cascaded) buffers I$
01
to I$
03
for illustrating the delay influence factors existing between each pair of adjacent buffers in the buffer chain. The delay influence factors “Cload” and “Trf” are a delay factor such as a dull of a waveform appearing when a voltage waveform inputted to or outputted from a circuit element is delayed because of the influence of the circuit element concerned and/or a preceding or succeeding circuit element. Precisely considering the delay time of a middle buffer I$
02
, the delay time of a middle buffer I$
02
is influenced by the delay influence factors “Cload” and “Trf” generated between the preceding buffer I$
01
and the buffer I$
02
when an input of the buffer I$
02
is connected to an output of the buffer I$
01
since the buffers I$
01
and I$
02
dynamically mutually influence each other, and the delay influence factor “Cload” generated between the buffer I$
02
and the succeeding buffer I$
03
when an output of the buffer I$
02
is connected to an input of the buffer I$
03
since the buffers I$
02
and I$
03
dynamically mutually influence each other. At the buffers at a boundary (node “a” and “b”) between the “Macro A” and the top layer, namely, at the buffer at a boundary of each of partial chains obtained by cutting out the buffer chain, these delay influence factors are not added in the delay calculation, and therefore, a delay amount caused by these delay influence factors is not propagated to a next buffer. As a result, an I/O path interconnection based on the delay influence (called an “interrelated delay” hereinafter) is not calculated, and accordingly, a correct delay value is not obtained at a boundary between different level layers in the hierarchical structure.
Therefore, it is demanded to calculate the correct delay value at a boundary between different level layers in the hierarchical structure.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a delay time calculating method for use in a hierarchical design, capable of calculating the correct delay value at a boundary between different level layers in the hierarchical structure.
In order to achieve the above and other objects of the present invention, the following delay time calculating method for use in a hierarchical design is provided in accordance with the present invention. In the following delay time calculating method in accordance with the present invention for use in a hierarchical design, the parenthesized reference signs corresponds to reference signs given in one or more embodiments of the present invention which will be described later with reference to the drawings, and added only for clarifying the relation between technical matters recited in the delay time calculating method in accordance with the present invention and constituents in the one or more embodiments of the present invention. Therefore, it should be noted that the parenthesized reference signs never limit the claimed invention to the embodiments of the present invention which will be described later with reference to the drawings.
According to the present invention, there is provided a delay time calculating method for use in a hierarchical design, the method comprising the steps of dividing a whole chain (T$
01
to T$
13
) to generate a first partial chain (T$
04
to T$
10
) and a second partial chain (T$
01
to T$
03
, T$
11
to T$
13
), calculating a first delay amount (TD(
4
-
10
)) of the first partial chain (T$
04
to T$
10
), generating a third partial chain (T$
01
to T$
05
, T$
09
to T$
13
) consisting of the second partial chain (T$
01
to T$
03
, T$
11
to T$
13
) and a plurality of chain elements (T$
04
to T$
05
, T$
09
to T$
10
) included in an end region of the first partial chain (T$
04
to T$
10
), calculating a second delay amount (TD(
1
-
5
), TD(
9
-
13
)) of the third partial chain (T$
01
to T$
05
, T$
09
to T$
13
), separating an end chain element (T$
05
, T$
09
) of the above mentioned plurality of chain elements (T$
04
to T$
05
, T$
09
to T$
10
) from the third partial chain (T$
01
to T$
05
, T$
09
to T$
13
) to calculate a third delay amount (D(
5
), D(
9
)) of the end chain element (T$
05
, T$
09
), subtracting the third delay amount (D(
5
), D(
9
)) from the second delay amount (TD(
1
-
5
), TD(
9
-
13
)) to obtain a fourth delay amount (TD(
1
-
4
), TD(
10
-
13
)), and overwriting the fourth delay amount (TD(
1
-
4
), TD(
10
-
13
)) to the first delay amount (TD(
4
-
10
)) in units of chain elements to calculate the delay amount (TD(
1
-
13
)) of the whole chain.
The calculation of the second delay amount (TD(
1
-
5
), TD(
9
-
13
)) is not accurate in connection with the calculation of the delay amount of the end chain element (T$
05
, T$
09
) of the above mentioned plurality of chain elements (T$
04
to T$
05
, T$
09
to T$
10
) included in the third partial chain (T$
01
to T$
05
, T$
09
to T$
13
). However, the fourth delay amount (TD(
1
-
4
), TD(
10
-
13
)) is accurate since it is obtained by subtracting from the second delay amount (TD(
1
-
5
), TD(
9
-
13
)) the third delay amount (D(
5
), D(
9
)), which is the delay time of the end chain element (T$
05
, T$
09
) of the above mentioned plurality of chain elements (T$
04
to T$
05
, T$
09
to T$
10
) included in the third partial chain (T$
01
to T$
05
, T$
09
to T$
13
). Furthermore, the delay amount of the end region (T$
04
, T$
10
) of the first partial chain (T$
04
to T$
10
) is also not accurate. However, this inaccuracy is removed by overwriting the fourth delay amount (TD(
1
-
4
), TD(
10
-
13
)) to the first delay amount (TD(
4
-
10
)) in units of chain elements. Thus, the accurate delay amount (TD(
1
-
13
)) of the whole chain can be obtained, and in the whole chain, the delay amount of the partial chain can be accurately obtained. The delay amount of the partial chain thus obtained can be utilized any times in the course of a simulation. In particular, the fo
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