Delay testing of high-performance digital components by a slow-s

Details Delay testing of high-performance digital components by a slow-s Delay testing of high-performance digital components by a slow-s

1994-10-21

1997-02-25

Beausoliel, Jr., Robert W.

Excavating

371 221, 371 251, 368113, G06F 1100

Patent

active

056065671

ABSTRACT:
High speed testing of a digital circuit may be performed although the rated frequency of the circuit exceeds the frequency capability of the test equipment. A digital circuit may be designed such that a controllable delay may be introduced in the timing paths of the circuit during testing using test stimuli which are applied at a clock rate that is less than the rated frequency of the circuit. By adding delay to the combinational signal path, testing of the circuit for operation at the maximum operating frequency is achieved during testing at a clock rate which is within the capability of the test equipment. The controllable delay may be incorporated as a delay element into a single-clock circuit and controlled by manipulation of the duty-cycle of a clock waveform which is applied to the circuit. The delay circuit is so designed that its function is also testable. In a multi-clock circuit, the delay is added to the circuit by skewing one clock signal with respect to the other clock signals.

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Agrawal, V. D., et al., "Built-in Self-test for Digital Integrated Circuits," New Electronic Test Technologies, AT&T Technical Journal, vol. 73, No. 2, Mar./Apr. 1994, pp. 30-39.

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