Delay test system for normal circuit

Details Delay test system for normal circuit Delay test system for normal circuit

2000-08-03

2003-06-03

Miska, Vit (Department: 2859)

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

C368S117000, C327S265000, C324S617000, C331S057000

Reexamination Certificate

active

06574169

ABSTRACT:

BACKGROUND OF THIS INVENTION
This invention relates to a delay test system of testing a normal circuit, such as an LSI.
Conventionally, a wide variety of tests have been performed to check whether or not each LSI is normally operated. In such tests, a delay test is included to test whether or not an undesirable delay takes place among logic circuits included in the LSI. To this end, a tester has been generally used to carry out the delay test of the LSI. In this event, the tester should generate a clock sequence of a high frequency and must have a very high performance. However, such a high performance tester is inevitably expensive.
On the other hand, it is a recent trend that an LSI is operated at a high speed and is therefore supplied with a very high frequency clock sequence. In order to test such an LSI operated at a high speed, a tester of the type described is also capable of supplying the LSI with a clock sequence of a high frequency. Otherwise, the delay test of such a high frequency LSI can not be preformed by the conventional tester of a low frequency. Under the circumstances, a delay test can not be practically performed by the use of the conventional tester.
Taking the above into consideration, some suggestions recently have been made about a method of performing the delay test with the tester having a low operation frequency. For instance, various methods have been disclosed in proceedings of International Test Conference 1995, page 302 to page 310, entitled “High-Performance Circuit Testing with Slow-Speed Testers”.
However, each of the testers should have a large amount of overhead with respect to the LSI structure. To avoid this, it is necessary to broadly change a conventional method of designing the LSI.
From this fact, it is readily understood that a conventional delay test method requires the high-speed tester. Further, when the high-speed tester is not required, a large amount of overhead is inescapably required to perform the delay test. Moreover, the method of designing the normal circuit must be also changed to effectively perform the conventional delay test in connection with a high speed LSI.
SUMMARY OF THIS INVENTION
It is therefore an object of this invention to provide a delay test method which is capable of performing a delay test of a LSI at a high speed with a tester having a low operation frequency without changing a design style of a normal circuit.
It is another object of this invention to provide an integrated circuit which is operable at a high speed and testable at a low frequency.
According to this invention, a delay test system includes a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit.
Further, a first clock input terminal is connected to the flip-flips and the normal circuit to input a normal clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal.
With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings of a normal clock signal during a normal operation on the condition that the second clock input terminal is halted.
On the other hand, the first and second clock input terminals are separately driven during the delay test. Consequently, the delay test is carried out by the use of a timing difference between a first edge timing of the normal clock signal and a second edge timing of the test clock signal.
More specifically, the flip-flop executes a single-phase synchronous operation during the normal operation while the flip-flop executes a double phase synchronous operation during the delay test operation.
In the event, the second clock input terminal is kept to a constant logic value in the single-phase synchronous operation. On the other hand, the first and second clock input terminals are separately driven in the double phase synchronous operation.
In this event, the design style of the normal circuit is invariable, and only the flip-flop is slightly changed so that there is no additional overhead.
Further, the result of the delay test is judged by the use of the timing difference between the clock edges. Consequently, the delay test can be carried out at a high speed without raising the frequency of the clock frequency of the tester.


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patent: 5818797 (1998-10-01), Wantanabe et al.
patent: 6233205 (2001-05-01), Wells et al.
patent: 6356514 (2002-03-01), Wells et al.
patent: 6452459 (2002-09-01), Chan et al.
patent: 6466520 (2002-10-01), Speyer et al.
patent: 6473455 (2002-10-01), Kwon

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