Delay test system for normal circuit

Details Delay test system for normal circuit Delay test system for normal circuit

1998-06-08

2000-10-03

Roskoski, Bernard

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

368113, G04F 800

Patent

active

061282537

ABSTRACT:
A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the teat clock signal in the test mode. Consequently, a delay test is carried out by the use of a timing difference between an edge timing of the normal mode clock signal and an edge timing of the test clock signal.

REFERENCES:
patent: 4613951 (1986-09-01), Chu
patent: 4995019 (1991-02-01), Begin
patent: 5796682 (1998-08-01), swapp
patent: 5818797 (1998-10-01), wantanabe et al.
Agrawal et al, "High-Performance Circuit Testing with Slow-Speed Testers" 1995, pp. 302-310, Paper 15.1 International Test Conference.

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