Delay test coverage without additional dummy latches in a scan-b

Details Delay test coverage without additional dummy latches in a scan-b Delay test coverage without additional dummy latches in a scan-b

1995-06-07

1996-08-06

Canney, Vincent P.

Excavating

371 225, 371 27, G06F 1100

Patent

active

055441734

ABSTRACT:
Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; sorting this list in the order of number of outputs controlled, i.e., touched in the forward trace; listing each unique combinational circuit output; sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs; when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.

REFERENCES:
patent: 5023875 (1991-06-01), Lee et al.
patent: 5187712 (1993-02-01), Malleo-Roach et al.
Waicukauski et al., "Latch Model Reduction Using Latch Behaviorals", IBM Technical Disclosure Bulletin, vol. 31, No. 9, Feb. 1989, pp. 471-473.
Hanna, "SRL Arrangement to Minimize Latches in LSSD Design", IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983, pp. 567-568.
Hanna, "LSSD Design Techniques", IBM Technical Disclosure Bulletin, vol. 27, No. 12, May 1985, pp. 7120-7123.

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