Delay test coverage enhancement for logic circuitry employing le

Details Delay test coverage enhancement for logic circuitry employing le Delay test coverage enhancement for logic circuitry employing le

1991-02-04

1994-01-11

Beausoliel, Jr., Robert W.

Excavating

371 221, H04B 1700

Patent

active

052788423

ABSTRACT:
By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines.

REFERENCES:
patent: 4736375 (1988-04-01), Tannhauser et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4802133 (1989-01-01), Kanuma et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4942577 (1990-07-01), Ozaki
IBM Technical Disclosure Bulletin, Delay Testing & Diagnosis of LSSD Shift Register Strings vol. 20 Nol. 1 (Jun. 1977) pp. 307-312.
IBM Technical Disclosure Bulletin, Bit-Pushing Approach to VLSI Circuit Self-Testing vol. 28, No. 2 (Jul. 1985) pp. 676-679.
IBM Technical Disclosure Bulletin, Shift Register Latch for Delay Testing vol. 32 No. 4A (Sep. 1989) pp. 231-232.
"Review of Built-in Test Methodologies for gale arrays" by K. A. E. Totten, IEEE Proceedings, vol. 132, Pts E & I, No. 2, Mar./Apr. 1985 pp. 121-129.
"Automated BIST for Sequential Logic Synthesis" by Charles E. Stroud, IEEE Design & Test of Computers, Dec. 1988, No. 6 pp. 22-32.

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