Delay stage with reduced V.sub.dd dependence

Details Delay stage with reduced V.sub.dd dependence Delay stage with reduced V.sub.dd dependence

1990-07-24

1991-11-26

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307451, 307579, 307585, 307576, 307594, 307482, 307578, 307448, H03K 513

Patent

active

050685538

ABSTRACT:
A delay stage (60) has a delay period of reduced dependence on the level of a first voltage supply (V.sub.dd). First and second inverter stages (78, 90) each have p-channel transistors (68, 86) and n-channel transistors (70, 88). The gates (64, 66) of the first inverter pair are connected to an input node (62). A fixed resistor (72) is inserted between the current path of the p-channel transistor (68) of the first inverter pair and a signal node (76). The current path of the n-channel transistor (66) of the first inverter is operable to connect the signal node (76) to ground. A MOSFET capacitor (80) is coupled to the signal node (76), as are the gates (82, 84) of the second inverter transistor (86, 88). The current path of the p-channel transistor (86) of the second inverter is operable to connect the voltage supply (V.sub.dd) to an output node (92), and the current path of the n-channel transistor (88) of the second inverter (90) is operable to connect the output node (92) to ground. The trigger point of the second inverter stage (90) is chosen to be substantially the same as the difference between the voltage supply level and the threshold voltage of the transistor (86).

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