Delay stage-interweaved analog DLL/PLL

Details Delay stage-interweaved analog DLL/PLL Delay stage-interweaved analog DLL/PLL

2006-12-12

2006-12-12

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C327S158000, C327S159000, C327S141000, C327S161000, C327S145000, C327S162000, C327S149000, C327S155000, C327S148000, C327S157000

Reexamination Certificate

active

07149145

ABSTRACT:
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

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John G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal, Nov. 1996, 1723-1732, vol. 31, No. 11.

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