Delay stage for a clock generator

Details Delay stage for a clock generator Delay stage for a clock generator

1980-09-10

1983-04-12

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307290, 307578, 307593, 307594, 307597, 307601, 307605, H03K 5135, H03K 3295, H03K 3356, H03K 17284

Patent

active

043799744

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to MOS integrated circuits, and more particularly relates to a clock generator and delay stage utilizing a Schmitt trigger release with a push-pull buffered output.


BACKGROUND ART

In the design of digital logic circuits, large scale integration techniques have brought about the construction of large numbers of components being fabricated on a single chip of silicon. In such circuitry, utilizing metal-oxide-semiconductor MOS techniques, random access memory devices have been fabricated. Such memories as well as other semiconductor circuitry utilize numerous clock signals generated by clock generators.
Clock generators for use with semiconductor data processing circuits are shown in U.S. Pat. No. 3,898,479 issued to Proebsting on Aug. 5, 1975 and entitled "Low Power, High Speed, High Output Voltage FET Delay-Inverter Stage" and U.S. Pat. No. 4,061,933 issued to Schroeder et al. on Dec. 6, 1977 and entitled "Clock Generator and Delay Stage". Such previous developed clock generators utilize a precharge input clock which necessitates an additional input to the clock generator circuit resulting in increased complexity as well as decreased performance and versatility.
With improved fabrication techniques, integrated circuits are made smaller in geometry of size; however, as the size of such circuits becomes smaller, the associate capacitance between circuit components does not similarly decrease. Overlap capacitance or Miller capacitance of transistor devices in such integrated circuits creates a substantial problem in affecting the response time of clock generators. The response time, in turn, determines, in part, how pattern insensitive the clock generator becomes to a quickly changing input voltage. Previously developed clock generators suffer in that with reduced geometries, Miller capacitance prevents the operation of such clock generators at desirable response times to operate independent of input voltage patterns. Furthermore, clock generators must operate independent of the rise time or slew rate of the input voltage signal.
A need has thus arisen for a clock generator for use in semiconductor circuitry which does not require a precharge input clock. Further, a need has arisen for a clock generator that operates independent of and is insensitive to input slew rates and input voltage patterns. Additionally, a need has arisen for a clock generator that has improved response times and fast reset times.


DISCLOSURE OF THE INVENTION

In accordance with the present invention, a clock generator is provided for random logic applications using MOS technology to substantially eliminate the problems heretofore associated with clock generators and which offers the advantages of insensitivity to input slew rates and voltage patterns without the need for a precharge input clock.
In accordance with the present invention, a delay stage for a clock generator circuit for providing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals is provided. A detector circuit is connected between the first and second power terminals and is connected to the input terminal for receiving the input signal. The detector circuit generates a detection signal upon detecting a predetermined level of the input signal. A buffer circuit is connected between the first power terminal and the detection circuit for receiving the detection signal and for generating the output signal at the output terminal.
In accordance with another aspect of the present invention, a clock generator circuit for producing clocking signals and which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals is provided. First, second and third transistors, each having drain, source and gate terminals are connected in series between the first power terminal and the second power terminal. A first node is formed betw

REFERENCES:
patent: 3898479 (1975-08-01), Proebsting
patent: 3984703 (1976-10-01), Jorgensen
patent: 4001722 (1977-01-01), Patel et al.
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4090096 (1978-05-01), Nagami
patent: 4122361 (1978-10-01), Clemen et al.
patent: 4242604 (1980-12-01), Smith
patent: 4250408 (1981-02-01), Spence
Yamaga et al., "Industrial Use C.sup.2 MOS IC", Toshiba Review, No. 95, pp. 20-25; 2/75.

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