Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-05-16
2002-07-16
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S235000
Reexamination Certificate
active
06420921
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay signal generating apparatus for generating a delay signal, and, in particular, to a delay signal generating apparatus used in a semiconductor testing apparatus.
2. Description of the Related Art
Development of semiconductor devices that can operate at high speed has recently flourished. This requires a semiconductor testing apparatus for testing such high-speed devices to have an ability to precisely control operation times. It is especially necessary to precisely delay a time at which an input pattern signal is input to a device to be tested with respect to a reference signal, depending on the input characteristics of the device to be tested.
FIG. 1
is a block diagram schematically showing a conventional variable delay circuit
10
that delays a reference signal
54
in order to generate a delay signal
74
having a predetermined delay time. The variable delay circuit
10
includes a minute variable delay portion
12
, a gate stage number change portion
14
, a linearizing memory
16
, an input terminal
18
and an output terminal
20
. The minute variable delay portion
12
includes a plurality of minute variable delay cells
12
a
,
12
b
, . . . ,
12
n
. The gate stage number change portion
14
includes a plurality of variable delay elements
14
a
,
14
b
,
14
c
, . . . ,
14
m
respectively having delay levels that change in a step-by-step manner. Each of the variable delay elements
14
a
,
14
b
,
14
c
, . . . ,
14
m
has a gate circuit with one or more stages and a selector. In the conventional variable delay circuit
10
, the reference signal
54
is input via the input terminal
18
, and the delay signal
74
is output via the output terminal
20
, after being delayed by a predetermined time period.
The gate stage number change portion
14
can change the delay time period by changing the number of gates through which the signal passes. Each of the variable delay elements
14
a
,
14
b
,
14
c
, . . . ,
14
m
typically has resolution that is set for a delay of 200 (ps) or more. The minute variable delay portion
12
obtains a delay-setting resolution that is smaller than the delay time period of a single stage of a gate.
The linearizing memory
16
stores delay data that is combinations of delay elements that can realize predetermined delay times (delay time periods), respectively, in predetermined addresses therein. In the case of using one or some of the minute variable delay cells
12
a
,
12
b
, . . . ,
12
n
and variable delay elements
14
a
,
14
b
,
14
c
, . . . ,
14
m
for obtaining a certain delay time period, for example, corresponding bits of the linearizing memory
16
are set to “1”. Other bits, each corresponding to the minute variable delay cell or variable delay element are set to “0”. Each of the minute variable delay cells
12
a
,
12
b
, . . . ,
12
n
and variable delay elements
14
a
,
14
b
,
14
c
, . . . ,
14
m
selects whether to delay a signal input thereto based on the delay data supplied from the linearizing memory
16
.
FIG. 2A
is a circuit diagram illustrating a variable driving impedance type minute variable delay cell
12
a
. In
FIG. 2A
, V
dd
denotes a positive power supply voltage and V
ss
denotes a negative power supply voltage. Either one of these power supply voltages can be used as ground. The delay data is supplied to a delay data terminal
26
from the linearizing memory
16
(see FIG.
1
). The minute variable delay cell
12
a
can change the delay time period for the input signal depending on a logical value of the delay data. More specifically, the driving impedance is set low when the logical value of the delay data is “0”, while the driving impedance is set high when the logical value of the delay data is “1”. Thus, when the delay data has the logical value of “1”, the input signal input to an input terminal
22
is delayed more than when the delay data has the logical value of “0”, and is then output from an output terminal
24
. The variable delay circuit
10
shown in
FIG. 1
can achieve a delay-setting resolution from about 10 (ps) to about 100 (ps) by providing the minute variable delay portion
12
as described above and the gate stage number change portion
14
.
FIG. 2B
is a circuit diagram illustrating a variable load capacitance type minute variable delay cell
12
a
. The delay data is supplied to a delay data terminal
26
from the linearizing memory
16
(see FIG.
1
). The minute delay cell
12
a
can change the delay time period for the input signal, depending on the logical value of the delay data. When the delay data has the logical value of “1”, the load capacitance is set. Thus, the input signal input to the input terminal
22
when the delay data has the logical value of “1” is delayed more than when the delay data has the logical value of “0”, and is output from the output terminal
24
. The variable delay circuit
10
shown in
FIG. 1
can achieve a delay-setting resolution from about 10 (ps) to about 100 (ps) by providing the minute variable delay portion
12
described above and the gate stage number change portion
14
.
The conventional variable delay circuit
10
shown in
FIG. 1
can be designed with a delay-setting resolution of
10
picoseconds or less, and several nanoseconds. In some cases, however, an error occurs between a designed delay time period and a delay time period actually provided by the delay element because of variation of self-heating of each delay element, change of ambient temperature, change in the power source voltage and the like.
FIG. 3
is a graph showing an example of delay characteristics of the variable delay circuit
10
. An axis of abscissas represents a delay time set in the variable delay circuit
10
while an axis of ordinates represents the actual delay time achieved by the variable delay circuit. A line
30
represents ideal delay characteristics of the variable delay circuit
10
. On the line of the ideal delay characteristics, the set delay time is equal to the actual delay time. A line
32
represents delay characteristics in a case where a propagation time period of the delay element is excessively long, while a line
34
represents delay characteristics in a case where the propagation time period of the delay element is excessively short.
Each of the lines
32
and
34
have errors with respect to the line
30
. One of the errors is a gain error. Moreover, the lines
32
and
34
have discontinuous portions that are non-linear errors, as is apparent from the graph. This is because the variable delay elements included in the variable delay circuit
10
are a plurality of different types, therefore the effects on the results of the variation of the element characteristics, the temperature change and the like do not always coincide with each other.
In order to compensate for the non-linearity of the delay characteristics, a method for measuring the delay time periods provided by all the combinations of the delay elements is applied in advance, and the delay elements are then re-arranged so as to obtain a desired delay characteristic. The measured data is stored in the linearizing memory
16
(see
FIG. 1
) and used during the test of the semiconductor device, i.e., the device to be tested.
In this case, it is necessary to prepare in advance a delay circuit having redundancy, considering factors causing the errors such as variation of the element characteristics, the fluctuation of the temperature or the power source voltage. When all possible factors causing errors are considered, the variation of the characteristics of typical semiconductor devices is approximately ±30%. This means that a ratio of the longest delay time period of a semiconductor device to the shortest delay time period thereof is 1.86 (130/70), that is, approximately double. Therefore, in order to produce a variable delay circuit
10
having a predetermined resolution and variable widths under all conditions, a number of redundant circuits are required, resulting in an increase
Okayasu Toshiyuki
Tsukahara Hiroshi
Advantest Corporation
Cox Cassandra
Rosenthal & Osha L.L.P.
Tran Toan
LandOfFree
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