Delay optimizing method in logic circuit designing

Details Delay optimizing method in logic circuit designing Delay optimizing method in logic circuit designing

1996-06-25

1998-06-09

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

057645280

ABSTRACT:
A delay optimizing method including a first step of detecting a signal path violating minimum delay constraints, a second step of calculating the frequency of overlap of each output terminal included in a synchronous sequential circuit with signal paths violating the minimum delay constraints, and a third step of inserting a level latch into a signal path in a descending order of the frequency of overlap with signal paths violating minimum delay constraints so as to have a minimum LSI layout pattern area of the synchronous sequential circuit.

REFERENCES:
patent: 5210700 (1993-05-01), Tom
patent: 5396435 (1995-03-01), Ginetti
patent: 5410491 (1995-04-01), Minami
patent: 5416718 (1995-05-01), Yamazaki
patent: 5557779 (1996-09-01), Minami
patent: 5638291 (1997-06-01), Li et al.
Shenoy et al., "Minimum Padding to Satisfy Short Path Constraints", pp. 156-161, (1993).

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