Delay optimization system to conduct optimization for satisfying

Details Delay optimization system to conduct optimization for satisfying Delay optimization system to conduct optimization for satisfying

1997-05-30

1999-12-28

Teska, Kevin J.

39550009, 3955001, 39550011, 39550012, 39550019, G06F 1750

Patent

active

060092483

ABSTRACT:
A delay optimization system including a layout processing unit for receiving the input of circuit specification of a target circuit to conduct layout, as well as extracting wiring information, an optimization processing unit for conducting optimization with reference to the wiring information, as well as generating circuit change information and inserted buffer information, and a constraints violations determining unit for determining whether a circuit generated as a result of the layout by the layout processing unit satisfies delay constraints set for the target circuit, the layout processing unit executing initial layout based only on circuit information synthesized based on the circuit specification of the target circuit and re-layout with reference to the circuit change information and inserted buffer information generated by the optimization processing unit.

REFERENCES:
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5727187 (1998-03-01), Lemche et al.
Sato et al "Post-Layout Omptimization for Deep Submicron Design," ACM, pp. 1-6, Jan. 1996.
Lillis et al "Optimal and Efficient Buffer Insertion and Wire Sizing," IEEE, pp. 259-262, Jan. 1995.
Kannan et al "A Methodoligy and Algorithms for Post-Placement Delay Optimization," ACM, pp. 327-332, Jan. 1994.
Bob Wiederhold "Deep-Submicron ASIC Design Requires Design Planning," EDN, pp. 95-100, Feb. 1995.
Barbara Tuck "Floorplanner Support Multiple Place-and-Route Tools, Block Generators," A Pennwall Publication, vol. 32, No. 4, p. 132, Apr. 1993.

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