Delay minimization for circuit emulation over packet...

Details Delay minimization for circuit emulation over packet... Delay minimization for circuit emulation over packet...

1998-12-23

2003-03-25

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S395430

Reexamination Certificate

active

06538995

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of minimizing delay in emulated circuits over packet switched networks.
2. Description of Related Art
Circuit emulation is the process of transporting a constant bit-rate (CBR) telecommunications service, such as T1, over packet switched networks such as asynchronous transfer mode (ATN) networks. The internet is to make the presence of the asynchronous network in the CBR communication path as transparent as possible. In addition to error-free transport of bits the circuit emulation must provide for transport of alarm, signaling and clock synhronization, thereby enabling the CDR service to be regenerated on exit from the asynchronous network in a manner that is fully complaint with pertinent standards.
In a perfect world, ATM cells for circuit emulation would be transmitted into an ATM network at equally-spaced intervals, and each cell would pass quickly through the network with minimal delay. However, one of the advantages of ATM is that it serves a wide variety of applications, many of which have little need for low transit delays. The co-existence of such applications can cause significant variation in the transit delay of cells through the network. Such delays are primarily a result of queues at points of congestion in the network. Whatever their cause, circuit emulation equipment for ATM networks must be designed to tolerate such delay variation.
When constant bit-rate (CBR) services are transported over an ATM network, a compromise must be drawn between tolerance of the cell delay variation (CDV) and the end-to-end delay. In particular, the device that receives ATM cells for circuit emulation applications must contain a buffer which, in the mean state, remains partially filled. Without such a buffer, a delayed cell will lead to starvation, where no data is available for the CBR transmitter. One must thus choose an operating point which maintains sufficient data in the buffer to accommodate CDV while at the same time keeping end-to-end delay at an acceptable level.
There are two other sources of variation in the buffer fill level that must be accommodated. Firstly, the buffer's fill-level plotted as a function of time looks like a saw-tooth because data are inserted into the buffer in cell-sized (53-byte) blocks but are drained from the buffer one bit at a time at a constant bit rate. Secondly, variation in the observed buffer fill level can be introduced by processing jitter, which is variability in the scheduling of buffer processing tasks caused by the sequencing and relative prioritization of other tasks performed by equipment within the network. Such processing jitter in the transmitting entity can cause variation in the time spacing between transmitted cells, which manifests itself as buffer fill-level variation in the receiving entity. Such processing jitter within the receiving entity can cause an apparent additional fill-level variation by introducing aperiodicity in the buffer management process.
The two additional sources of buffer fill-level variation are generally less problematic than CDV. Processing jitter is under the control of the system designer and can be reduced to a manageable level by proper design, and the “saw-tooth” effects can be minimized by roughly synchronizing the sampling of the buffer's fill-level with the arrival of ATM cells.
The standard approach for accommodating CDV in circuit emulation equipment is to choose a fixed target mean buffer fill level in the entity that receives ATM cells from the network. This target mean buffer fill level is chosen to accommodate the anticipated worst-case variation in buffer fill level, i.e., the target must be high enough to prevent the buffer from ever being emptied when cells encounter worse-case delays. This approach is unduly conservative if the preconceived notion of worst-case delay is too high, and more delay is introduced than is actually needed for safe system operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved means of trading off throughput delay for tolerance of cell-delay variation (CDV) in circuit emulation over ATM Networks.
According to the present invention there is provided a method of minimizing throughput delay in constant-bit-rate services carried over packet-based networks subject to variable delays, comprising the steps of receiving incoming packets in a buffer, reading out bits from the buffer at a clock frequency f
i
, continually monitoring the buffer fill level L
i
, determining the minimum fill level Lmin
k
over a plurality k of successive samples, and adjusting the clock frequency f
i
to cause the minimum fill level Lmin
k
to tend toward a predetermined set-point TargetLmin.
In one embodiment, the clock frequency is adjusted by causing the maximum fill level Lmax
j
of the buffer to tend toward a target value TargetLmax, and adaptively changing said target value TargetLmax so that the minimum fill level Lmin
k
tends toward said predetermined set-point, the rate of change of the target value TargetLmax being significantly slower than the rate of adjustment of clock frequency.
The invention obviates the need for identifying a fixed safe operating point, and automatically moves to a lower-delay operating point when the network's performance indicates that it is possible to do so. In particular, the prior art method is to choose a fixed mean buffer fill level. This method makes an implicit assumption that excursion of the buffer fill level about its mean very rarely exceeds this chosen set-point. To achieve this, one generally has an intuitive notion as to the size of the worst-case excursion and then chooses a set-point that accommodates such an excursion. The invention is different in that it monitors the minimum buffer fill level rather than the mean. It is thus no longer necessary to make assumptions about the worst-case excursion. This means that the system gravitates towards a lower-delay operating point when it possible to do so, i.e., when the preconceived estimate of the worst-case excursion is unduly pessimistic.
The invention also provides an apparatus for providing constant-bit-rate services in packet-based networks subject to variable delays with minimum throughput delay, comprising a buffer for receiving incoming packets in a buffer, means reading out bits from the buffer at a clock frequency fj, means for continually monitoring the buffer fill level Li, means for determining the minimum fill level Lmin
k
over a plurality of successive samples, and means for adjusting the clock frequency fj to cause the minimum fill level Lmin
k
to tend toward a setpoint TargetLmin.


REFERENCES:
patent: 4759014 (1988-07-01), Decker et al.
patent: 4961188 (1990-10-01), Lau
patent: 5204882 (1993-04-01), Chao et al.
patent: 5396492 (1995-03-01), Lien
patent: 5812618 (1998-09-01), Muntz et al.
patent: 5844891 (1998-12-01), Cox

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