Delay measuring circuit

Electrical transmission or interconnection systems – With nonswitching means responsive to external nonelectrical... – Temperature responsive

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Details

307518, 328 55, 328133, 377 20, 377 56, H03K 514, H03K 5153

Patent

active

050497669

ABSTRACT:
In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

REFERENCES:
patent: 4330751 (1982-05-01), Swain
patent: 4623805 (1986-11-01), Flora et al.
patent: 4637018 (1987-01-01), Flora et al.
patent: 4754164 (1988-06-01), Flora et al.
patent: 4755704 (1988-07-01), Flora et al.
patent: 4777385 (1988-10-01), Hartmeier
patent: 4968907 (1990-11-01), Pepper
patent: 4979194 (1990-12-01), Kawano

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