Delay matching circuit

Details Delay matching circuit Delay matching circuit

1993-04-05

1994-12-27

Skudy, R.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

331 1A, 327156, 327281, 326 95, H03K 3366, H03K 5135

Patent

active

053768485

ABSTRACT:
A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.

REFERENCES:
patent: 4689581 (1987-08-01), Talbot
patent: 4839541 (1989-06-01), Gal et al.
patent: 4843254 (1989-06-01), Motegi et al.
patent: 4933571 (1990-06-01), Pribyl
patent: 5212410 (1993-05-01), Sase

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