Delay locked loop with reduced noise response

Details Delay locked loop with reduced noise response Delay locked loop with reduced noise response

2001-06-29

2002-08-13

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06433597

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and, more particularly, to a delay locked loop with reduced noise response.
BACKGROUND OF THE INVENTION
Generally, a delay locked loop is a circuit which can be used to match an internal clock of a synchronous memory with an external clock without error. In other words, by controlling a time delay of the internal clock relative to the external clock, the internal clock is synchronized with the external clock.
FIG. 1
is a block diagram of a conventional delay locked loop. Referring to
FIG. 1
, the illustrated conventional delay locked loop comprises a first clock buffer
100
for receiving an external clock bar CLKb for producing a falling clock signal FCLKT
2
which is activated at a falling edge of a clock. It also includes a second clock buffer
110
for receiving an external clock CLK for producing a rising clock signal RCLKT
2
activated at a rising edge of the clock. The delay locked loop of
FIG. 1
also includes a clock divider
120
for producing a pulse at every eight clocks of the rising clock signal RCLKT
2
and a phase comparator
130
for comparing a reference signal REF from the clock divider
120
with a feedback signal FEEDBACK from a delay modeling circuit
190
. In addition, it includes a shift controller
140
for receiving the output of the phase comparator
130
to produce a right shift signal SR and a left shift signal SL for shifting a shift register
150
. The shift register
150
controls the delay amount by shifting an output signal with the right shift signal SR and the left shift signal SL. The delay locked loop also includes a first delay line
160
responsive to the output signal of the shift register
150
for adjusting the delay amount of the output signal of the clock divider
120
, a second delay line
170
responsive to the output signal of the shift register
150
for adjusting the delay amount of the rising clock signal RCLKT
2
, and a third delay line
180
responsive to the output signal of the shift register
150
for adjusting the delay amount of the falling clock signal FCLKT
2
. The delay modeling circuit
190
compensates the time difference between the external clock and the internal clock by using a feedback delay signal FEEDBACK_DLY
1
received from the first delay line
160
. The device of
FIG. 1
also includes a delay locked loop signal driver
200
for driving internal circuitry with the second and third delay lines
170
and
180
.
In operation, the clock divider
120
receives the rising clock signal RCLKT
2
and produces the reference signal REF and a delay line input signal DELAY_IN that is synchronized with the rising clock signal at every other eight clocks. The reference signal REF is used as a reference for comparison with the feedback signal, which models the time delay to compensate and is feedback from the delay modeling circuit
190
. The delay line input signal DELAY_IN is applied to the first delay line
160
and undergoes the delay adjusted by the shift register
150
to enable the feedback signal FEEDBACK through the delay modeling circuit
190
. The feedback signal FEEDBACK is compared with the rising edge of the reference signal REF at the phase comparator
130
. The shift controller
140
outputs the right shift signal SR or the left shift signal SL depending on the comparison result.
FIG. 2
provides a detailed circuit diagram of the conventional phase comparator
130
and the conventional shift controller
140
. Referring to
FIG. 2
, the illustrated conventional phase comparator
130
includes: (a) a first comparator
210
for comparing the reference signal REF with the feedback signal FEEDBACK to produce first and second phase comparison signals PC
0
and PC
1
, (b) a unit delay circuit
220
for delaying the feedback signal FEEDBACK by a unit delay, (c) a second comparator
230
for comparing the reference signal REF with the output signal of the unit delay circuit
220
to produce second and fourth phase comparison signals PC
1
and PC
3
, and (d) a pulse generator
240
for receiving the reference signal REF and the feedback signal FEEDBACK to generate a comparison pulse signal CMP_PULSE.
Referring to
FIG. 2
, the illustrated conventional shift controller
140
includes: (a) a first NAND gate
250
which receives the first phase comparison signal PC
0
and the third phase comparison signal PC
2
, (b) a first inverter
255
receiving the output of the first NAND gate
250
, (c) a second NAND gate
260
receiving the second phase comparison signal PC
1
and the fourth phase comparison signal PC
3
, (d) a second inverter
265
receiving the output of the second NAND gate
260
, (e) a third NAND gate
270
receiving the output of the first inverter
255
and the comparison pulse signal CMP_PULSE, (f) a third inverter
275
receiving the output of the third NAND gate
270
to output the right shift signal SR, (g) a fourth NAND gate
280
receiving the output of the second inverter
265
and the comparison pulse signal CMP_PULSE, (h) a fourth inverter
285
receiving the output of the fourth NAND gate
280
to output the left shift signal SL, (i) a NOR gate
290
receiving the right shift signal SR and the left shift signal SL, and (j) a fifth inverter
295
receiving the output of the NOR gate
290
to output the delay locked loop locking signal DLL_LOCKZ.
The phase comparator
130
and the pulse generator
240
generate pulses when the reference signal REF and the feedback signal FEEDBACK are simultaneously high. When this comparison pulse signal CMP_PULSE is activated, the shift controller
140
receives the first to fourth phase comparison signals PC
0
, PC
1
, PC
2
and PC
3
from the phase comparator
130
to output the right shift signal SR and/or the left shift signal SL.
The right shift signal SR and/or the left shift signal SL operate the shift register
150
so as to control the delay amount. Repeating as described above, the delay locked loop clock is generated at locking at which the reference signal REF and the feedback signal FEEDBACK have a minimum jitter.
Receiving the delay locked loop clock generated as described above, data is transferred to outside of a chip through an output buffer, wherein the difference between the output data DQ and the external clock is referred to as an AC parameter tAC (DQ edge to clock edge skew).
The phase comparator
130
compares the reference signal REF and the feedback signal FEEDBACK at every eight clocks even after the delay locked loop clock is generated so as to shift the shift register when there is a difference between the reference signal REF and the feedback signal FEEDBACK.
Accordingly, the phase comparator
130
compares the difference between the reference signal REF and the feedback signal FEEDBACK and generates a corresponding output even if the difference is generated by noise, which could cause undesirable shift operation of the shift register
150
.
When data is outputted by using the delay locked loop clock with the delay amount readjusted due to noise and the number of stages of the unit delay of the loop is changed, the AC parameter tAC suffers a loss corresponding to the number of the changed stages of the unit delay.


REFERENCES:
patent: 4789966 (1988-12-01), Butcher
patent: 6075832 (2000-06-01), Geannopoulos et al.

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