Delay locked loop with precision controlled delay

Details Delay locked loop with precision controlled delay Delay locked loop with precision controlled delay

2003-12-10

2008-11-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S268000, C327S283000, C327S290000

Reexamination Certificate

active

07456664

ABSTRACT:
The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.

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Eto et al.,A 333MHz, 20mW, 18ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC(PVR-DAC), Proceedings of the Second IEEE Asia Pacific Conference on Asics, 2000, pp. 349-350.

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