Delay locked loop with immunity to missing clock edges

Details Delay locked loop with immunity to missing clock edges Delay locked loop with immunity to missing clock edges

2000-05-15

2001-07-17

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S158000

Reexamination Certificate

active

06262608

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of analog circuit design. More particularly, the invention relates to an apparatus and method for ensuring the proper operation of a delay locked loop, even in the presence of missing clock edges.
2. Description of the Related Art
For years, delay locked loops (“DLLs”) have been used extensively in the field of analog circuit design. More recently, with the increasingly stringent timing requirements of high performance computing and communications systems today, DLLs are frequently being employed in digital circuit designs (e.g., computer motherboards, high performance multimedia boards, intelligent wireless devices . . . etc).
The design goal of a DLL is to generate a clock which is delayed by a specified number of clock periods with respect to the input clock. For this reason, DLLs are commonly used in applications which require clock-skew elimination, clock/data recovery and multi-phase clock generation.
FIG. 1
illustrates a block diagram of a traditional DLL circuit. The input clock
105
, passes through a voltage controlled delay line (“VCDL”)
110
which generates a delayed version (CLK
out
)
120
of the input clock
105
. The delay in the VCDL
110
must be set precisely to some multiple of the input clock
105
period (e.g., 2×, 3×, etc., depending on the application). The delay through the VCDL
110
is controlled by a control voltage
115
. The higher the control voltage
115
, the shorter the delay between the input and output clocks.
The control voltage
115
(and, therefore, the amount of delay in the VCDL
110
) is modified by a feedback loop which consists of a phase detector
125
, a charge pump
130
and a capacitor
135
. The phase detector
125
detects the actual time delay (i.e., the phase difference) between the input clock
105
and the output clock
120
and, in response, causes the charge pump
130
to generate either a positive or a negative current pulse. A positive pulse charges the capacitor
135
, increasing the control voltage
115
, and a negative pulse discharges the capacitor
135
, decreasing the control voltage
115
. Accordingly, if the delay of the output clock
120
is too high, the charge pump
130
provides a positive current pulse (increasing the control voltage
115
), and if the delay is too short, the charge pump
130
provides a negative current pulse (decreasing the control voltage). The feedback loop will settle when the delayed clock
120
is at the desired phase multiple of the input clock
105
(i.e. the delay is 1, 2, 3, etc. input clock periods).
While DLLs have the advantage of lower order transfer functions (hence having high stability with relatively low jitter), it is important that DLLs be started in a known state to ensure that the delayed clock is locked to exactly one reference clock period (or ‘n’ clock periods, depending on the application). A missing clock edge can cause the phase detector
125
to force the DLL to lock to an incorrect delay which is a multiple of this period (or “zero” delay). In this case, the delayed clock edges may appear to be aligned with the reference clock edges when, in reality, they are improperly skewed by one or more clock periods.
SUMMARY OF THE INVENTION
A method for determining whether to trigger a reset of a delay locked loop (“DLL”) comprising calculating the difference in time between a reference clock and a delayed clock; comparing the difference in time to the amount of time required for a reset signal to reset said DLL; and generating the reset signal to reset the DLL if the reset time is less than the difference in time between the reference clock and the delayed clock.


REFERENCES:
patent: 4503536 (1985-03-01), Panzer
patent: 4542354 (1985-09-01), Robinton, et al.
patent: 4805192 (1989-02-01), Confalonieri, et al.
patent: 4974184 (1990-11-01), Avra
patent: 5202978 (1993-04-01), Nozuyama
patent: 5317283 (1994-05-01), Korhonen
patent: 5561660 (1996-10-01), Kotowski, et al.
patent: 5721547 (1998-02-01), Longo
patent: 5854575 (1998-12-01), Fiedler, et al.
patent: 5936900 (1999-08-01), Hii, et al.
patent: 6066988 (2000-05-01), Igura
“Optimization of Phase-Locked Loop Performance In Data Recovery Systems”, Ramon S. Co & J.H. Mulligan, Jr., IEEE Journal of Solid—State Circuits, vol. 29, No. 9, 09/94, pp. 1022-1033.
“Basic Opamp Design and Compensation”, David Johns, et al., pp. 221-225, 1997.
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, John G. Maneatis, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, 11/96, pp. 1723-1732.
“Monolithic Phase-Locked Loops And Clock Recovery Circuits: Theory and Design”, Behzad Razavi, 1996, pp. iii-xi and 1-498.
“A 155-MHz Clock Recovery Delay-and Phase-Locked Loop”, Thomas H. Lee, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1736-1745.

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