Delay locked loop with frequency control

Details Delay locked loop with frequency control Delay locked loop with frequency control

2008-01-15

2008-01-15

Payne, David C. (Department: 2611)

Pulse or digital communications

Synchronizers

C375S362000, C375S371000, C375S373000, C375S376000, C327S147000, C327S149000, C327S154000, C327S156000, C327S155000

Reexamination Certificate

active

07319728

ABSTRACT:
A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.

REFERENCES:
patent: 3955158 (1976-05-01), Upadhyayula et al.
patent: 3993957 (1976-11-01), Davenport
patent: 5691660 (1997-11-01), Busch et al.
patent: 5717353 (1998-02-01), Fujimoto
patent: 5930182 (1999-07-01), Lee
patent: 5946244 (1999-08-01), Manning
patent: 6002281 (1999-12-01), Jones et al.
patent: 6081462 (2000-06-01), Lee
patent: 6085345 (2000-07-01), Taylor
patent: 6088255 (2000-07-01), Matsuzaki et al.
patent: 6108793 (2000-08-01), Fujii et al.
patent: 6172537 (2001-01-01), Kanou et al.
patent: 6181174 (2001-01-01), Fujieda et al.
patent: 6184753 (2001-02-01), Ishimi et al.
patent: 6219384 (2001-04-01), Kliza et al.
patent: 6275079 (2001-08-01), Park
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 6313676 (2001-11-01), Abe et al.
patent: 6316976 (2001-11-01), Miller, Jr. et al.
patent: 6374360 (2002-04-01), Keeth et al.
patent: 6378079 (2002-04-01), Mullarkey
patent: 6381194 (2002-04-01), Li
patent: 6385129 (2002-05-01), Silvestri
patent: 6388480 (2002-05-01), Stubbs
patent: 6414903 (2002-07-01), Keeth et al.
patent: 6421789 (2002-07-01), Ooishi
patent: 6421801 (2002-07-01), Maddux et al.
patent: 6438060 (2002-08-01), Li
patent: 6446180 (2002-09-01), Li et al.
patent: 6456130 (2002-09-01), Schnell
patent: 6476653 (2002-11-01), Matsuzaki
patent: 6492852 (2002-12-01), Fiscus
patent: 6600912 (2003-07-01), Stepp et al.
patent: 6605969 (2003-08-01), Mikhalev et al.
patent: 6621317 (2003-09-01), Saeki
patent: 6771103 (2004-08-01), Watanabe et al.
patent: 6876594 (2005-04-01), Griesmer et al.
patent: 6937076 (2005-08-01), Gomm
patent: 7212057 (2007-05-01), Gomm et al.
patent: 2002/0017939 (2002-02-01), Okuda et al.
patent: 2002/0130691 (2002-09-01), Silvestri
patent: 2003/0011414 (2003-01-01), Bell
patent: 2003/0012320 (2003-01-01), Bell
patent: 2003/0179639 (2003-09-01), Bell et al.
patent: 2003/0214334 (2003-11-01), Gomm et al.
patent: 2003/0214338 (2003-11-01), Silvestri
patent: 2003/0215040 (2003-11-01), Bell et al.
patent: 2005/0242850 (2005-11-01), Kawasaki
patent: 2006/0250859 (2006-11-01), Bell et al.
patent: 2007/0075763 (2007-04-01), Gomm et al.
Tamura et al, “SA 20.7: Partial Response Detection Technique for Driver Power REduction in High-Speed Memory-to-Processor Communications”, 1997 IEEE International Solid-State Circuits Conference, pp. 342-343,348.
Jang, Seong-Jin , et al., “A Compact Ring Delay Line for High Speed Synchronous DRAM”,IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers, (Jun. 11-13, 1998), pp. 60-61.
Kim, Jae J., et al., “A low-jitter mixed-mode DLL for high-speed DRAM applications”,IEEE Journal of Solid State Circuits, 35(10), (Oct. 2000), pp. 1430-1436.
U.S. Appl. No. 10/147,657 Non-Final Office Action mailed May 8, 2003, 10 pgs.
U.S. Appl. No. 10/147,657 Notice of Allowance mailed Nov. 4, 2003, 7 pgs.
U.S. Appl. No. 10/147,657 Notice of Allowance mailed Mar. 9, 2004, 7 pgs.
U.S. Appl. No. 10/147,657 Notice of allowance mailed May 18, 2004, 7 pgs.
U.S. Appl. No. 10/147,657 Response filed Aug. 8, 2003 to Office Action mailed May 3, 2003, 14 pgs.
U.S. Appl. No. 10/771,611 Non-final office action mailed Oct. 19, 2005, 9 pgs.
U.S. Appl. No. 10/771,611 Non-final office action mailed Mar. 23, 2005, 11 pgs.
U.S. Appl. No. 10/771,611 Non-final office action mailed Apr. 5, 2006, 7 pgs.
U.S. Appl. No. 10/771,611 Notice of allowance mailed Sep. 7, 2006, 8 pgs.
U.S. Appl. No. 10/771,611 Response filed Jul. 25, 2005 to non-final office action mailed Mar. 23, 2005, 16 pgs.
U.S. Appl. No. 10/771,611 Response filed Jul. 5, 2006 to non final office action mailed Apr. 5, 2006, 14 pgs.
U.S. Appl. No. 11/606,757 Notice of Allowance mailed Jul. 12, 2007, 8 pgs.
U.S. Appl. No. 11/606,757 Response filed Jun. 20, 2007 to Office Action received Apr. 23, 2007, 11 pgs.

Affiliated with

Also associated with

Rating

Delay locked loop with frequency control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay locked loop with frequency control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop with frequency control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2814726