Delay locked loop with a function for implementing locking...

Details Delay locked loop with a function for implementing locking... Delay locked loop with a function for implementing locking...

2008-06-17

2008-06-17

Garber, Charles D. (Department: 4125)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S159000

Reexamination Certificate

active

07388415

ABSTRACT:
A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in response to some of a plurality of global clock signals, a phase detection signal, and a power down signal, outputs an input clock signal to each of the global clock generator and the clock delay unit. During the power down mode, the clock delay unit is enabled to periodically carry out the locking operation whenever it receives the input clock signal. Therefore, a consumed power of the DLL can be decreased during the power down mode, and a phase difference between an external clock signal and an internal clock signal during the power down mode can be decreased by the periodical locking operation of the clock delay unit, so that the DLL can operate at a fast speed after the power down mode.

REFERENCES:
patent: 2003/0140318 (2003-07-01), Kitahara et al.
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Korean Notice of Allowance for 2006-15011.

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