Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Reexamination Certificate
2000-10-19
2003-08-19
Patel, Rajnikant B. (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
C257S723000
Reexamination Certificate
active
06608743
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a delay locked loop, a synchronizing method for the delay locked loop and a semiconductor device equipped with the delay locked loop. Particularly, this invention relates to a delay locked loop that allows an internal clock, which is obtained delaying an external clock supplied from outside by a given delay time, to be synchronized with the external clock.
BACKGROUND OF THE INVENTION
One of typical methods of operating a large-scale and complex digital circuit with good stability and efficiency is synchronous circuit designing that allows all logic cells (flip flop (FF), latch etc.) in the digital circuit to operate synchronizing with one clock. Semiconductor devices such as large-scale integrated circuit (LSI), very-large-scale integrated circuit (VLSI) and ultra-large-scale integrated circuit also have one digital circuit formed on the chip, and they are designed mostly by the synchronous circuit designing.
In order to lead a digital circuit designed by such synchronous circuit designing to accurate operation, all logic cells need to operate at the same timing. This is because, if there is a gap between clocks that are input to the respective logic cells, a problem described below occurs. For example, when multiple FFs cascade-connected compose a shift register, if the rise or fall of clock input to a subsequent FF slightly gets behind the rise or fall of clock input to the previous FF, the output data of the previous FF changes in the instant that the subsequent FF is going to take the output data of the previous FF. Therefore, the subsequent FF may incur a malfunction, for example, data that is due to delay by one cycle maybe, without delay, output from the subsequent FF. Such a phenomenon is called racing.
Also in synchronous semiconductor storage, responding to data reading command to be sent from CPU, data is read synchronizing with an internal clock that is generated synchronizing with an external clock supplied from outside. However, if out of synchronization, the PCU fails to accurately read data, therefore the CPU and the entire system will be subjected to a malfunction.
In recent years, the number of logic cells composing a semiconductor device increases as the integration density and operation speed of a semiconductor device such as LSI increases. When a digital circuit is formed on chip of such a semiconductor device, the number of logic cells to operate simultaneously increases. Therefore, the risk of occurrence of the above-mentioned racing and an error in data reading becomes high.
Because of this, recently, produced are semiconductor devices that a phase-adjusting circuit such as phase locked loop (PLL) or delay locked loop (DLL) is installed so that a clock supplied to all logic cells is synchronized with an external clock supplied from outside or an internally-generated clock supplied from an internal clock generating means.
PLL is, for example, composed of a phase comparison circuit, a low-pass filter (LPF) and a voltage-controlled oscillator (VCO). The phase comparison circuit compares a phase of the external clock or internally-generated clock with a phase of internal clock supplied from the VCO, and outputs a phase error signal according to its phase error. The LPF smoothes the phase error signal, and outputs it as control voltage. The VCO oscillates at an internal clock based on the control voltage, and supplies the internal clock to the phase comparison circuit.
DLL is, for example, composed of a phase comparison circuit, a delay circuit and an LPF. The phase comparison circuit compares a phase of the external clock or internally-generated clock with a phase of internal clock supplied from the VCO, and outputs a phase error signal according to its phase error. The LPF smoothes the phase error signal, and outputs it as control voltage. The delay circuit makes the external clock or internally-generated clock delay based on the control voltage, and supplies it as an internal clock to the phase comparison circuit.
Since, of these phase-adjusting circuits, the DLL is not equipped with especially the VCO as installed in the PLL, the DLL allows the phase adjusting circuit to be composed with fewer number of elements and low power consumption.
FIG. 1
is a block diagram showing an example of partial composition of semiconductor device equipped with a conventional DLL.
In this example, the semiconductor device is composed of a phase comparison circuit
1
, a counter
2
, a digital-to-analogue converter (DAC)
3
, a delay circuit
4
, flip flops (FF)
5
and
6
, buffers and
8
, and an output dummy circuit
9
.
The phase comparison circuit
1
compares a phase of external lock ECK supplied from outside with a phase of dummy data DDT supplied from the output dummy circuit
9
. When the phase of external clock ECK is behind the phase of dummy data DDT, the phase comparison circuit
1
outputs an up clock UCK with pulses of number according to the phase difference, to the counter
2
. When the phase of external clock ECK is ahead of the phase of dummy data DDT, the phase comparison circuit
1
outputs a down clock DCK with pulses of number according to the phase difference, to the counter
2
.
The counter
2
outputs a count value CT to be counted up or counted down according to the up clock UCK or down clock DCK supplied from the phase comparison circuit
1
, to the DAC
3
.
The DAC
3
converts the count value CT supplied from the counter
2
into analogue delay voltage V
D
, and supplies it to the delay circuit
4
.
The delay circuit
4
allows the delay time to be changed according to the delay voltage V
D
supplied from the DAC
3
, and delays the external clock ECK by that delay time, then outputting it as an internal clock ICK. The range of the delay time changed in the delay circuit
4
is set to be at least one cycle of the external clock ECK. For example, when the frequency of the external clock ECK is 100 MHz, the range of changing is set to be 0 to 10 ns.
FIG.2
shows an example of composition of the delay circuit
4
. The delay circuit
4
is composed of inverters
11
to
14
, N-channel FETs
15
to
17
and capacitors
18
to
20
. The inverters
11
to
14
are cascade-connected, and the external clock ECK is applied to the input of the inverter
11
and the internal clock ICK is output from the output of the inverter
14
. The respective gates of the FETs
15
to
17
are connected each other, and delay voltage V
D
is applied to the gates. The FET
15
has the source connected to the connection point between the output of the inverter
11
and the input of the inverter
12
, and has the drain connected to one end of the capacitor
18
, the other end of the capacitor
18
being grounded. Similarly, the FET
16
has the source connected to the connection point between the output of the inverter
12
and the input of the inverter
13
, and has the drain connected to one end of the capacitor
19
, the other end of the capacitor
19
being grounded. The FET
17
has the source connected to the connection point between the output of the inverter
13
and the input of the inverter
14
, and has the drain connected to one end of the capacitor
20
, the other end of the capacitor
20
being grounded.
Since the delay time of the delay circuit
4
cannot be shorter than the sum of the delay times of the four inverters
11
to
14
, if the phase of external clock ECK is ahead of the phase of dummy data DDT, by delaying the phase of internal clock ICK by amount of phase obtained subtracting the phase being advanced from the phase of one cycle, the phase of external clock ECK is made to coincide with the phase of dummy data DDT, i.e., the phase of internal clock ICK. For example, when the frequency of external clock ECK is 100 MHz, one cycle is 10 ns. Given that the sum of the delay times of the four inverters
11
to
14
is, for example, 5 ns, when the count number CT of the counter
2
is five and the delay voltage is 0.5 V, the delay time of the delay circuit
4
is further increased by 5 ns, thereby being
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Patel Rajnikant B.
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