Delay locked loop structure providing first and second...

Details Delay locked loop structure providing first and second... Delay locked loop structure providing first and second...

2007-04-03

2007-04-03

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

11230896

ABSTRACT:
A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal over a second frequency range. The second circuit is configured to signal the first circuit to lock onto the clock signal to provide the second locked clock signal as the frequency changes from the first frequency range to the second frequency range. Also, the second circuit is configured to signal the first circuit to provide a locked one of the first locked clock signal and the second locked clock signal in a locked output clock signal.

REFERENCES:
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6100735 (2000-08-01), Lu
patent: 6340904 (2002-01-01), Manning
patent: 6490224 (2002-12-01), Manning
patent: 6809600 (2004-10-01), Chang et al.
patent: 7099424 (2006-08-01), Chang et al.

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