Delay locked loop incorporating a ring type delay and...

Details Delay locked loop incorporating a ring type delay and... Delay locked loop incorporating a ring type delay and...

2001-06-25

2002-08-20

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S236000

Reexamination Certificate

active

06437618

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a delay locked loop having the ability to operate in low frequency applications.
BACKGROUND OF THE INVENTION
In general, a delay locked loop (DLL) circuit reduces the skew between a clock signal and a data signal or between an external clock and an internal clock. In this latter example, a DLL is used in synchronizing an internal clock of a synchronous memory to an external clock to avoid signal timing errors. Specifically, as a timing delay occurs when using an external clock with a system, the delay locked loop adjusts the timing delay to synchronize the internal clock of the system to the external clock.
FIG. 1
is a schematic block diagram of a conventional linear register controlled digital delay line (DDL). Specifically, a synchronous DRAM memory application having a delay locked loop
500
and other peripheral circuits is shown. The conventional delay locked loop
500
comprises an input unit
100
, a delay monitor
110
, a phase detection unit
120
, a shift register
130
, and a digital delay line
140
.
The input unit
100
receives an external clock signal CLK and produces a delay lock loop clock input signal CLKin. The delay monitor
110
receives an output signal CLKout generated by the delay locked loop
500
to monitor any time delay between the clock input signal CLKin and the clock output signal CLKout. The phase detection unit
120
receives the clock input signal CLKin from the input unit
100
and the output signal from the delay monitor
110
and determines the difference in phase between these received signals. Based on the phase difference, the detection unit
120
produces a shift control signal. The shift control signal can be a left shift signal or a right shift signal. The shift register
130
controls the adjustment of the time delay, based on the shift control signal from the phase detection unit
120
. The digital delay line
140
adjusts the time delay according to the output of the shift register
130
.
In this example, data read by a DRAM core block
150
is synchronous with the clock output signal CLKout, and a synchronized signal is outputted through a D-flip flop
160
and an output driver unit
170
. When the delay locked loop
500
is not in use, i.e., when the clock input signal CLKin and the clock output signal CLKout are synchronous in phase, the final output data DQ is skewed from the external clock signal, where the skew corresponds to a time delay t
R
introduced at the input unit
100
(as shown) plus a time delay t
D
introduced between the D-flip flop
160
and the output drive unit
170
(as shown). Accordingly, the use of the delay locked loop shown in
FIG. 1
allows the final output data DQ to be synchronized with the external clock signal. To achieve this synchronization, the clock input signal CLKin is delayed by a certain time period.
FIG. 2
is a detailed block diagram of the conventional digital delay line
140
that is used to adjust the above-described delay. The digital delay line
140
includes a control unit
200
for outputting the clock input signal CLKin fed thereto from the input unit
100
based on three shift signals (s
1
, s
2
, s
3
), received from the shift register
130
. The digital delay line
140
also includes a delay block
210
for performing a time delay on the clock input signal CLKin under the control of the control unit
200
and an output unit
220
for outputting a time-delayed signal from the delay block
210
as the clock output signal CLKout. Specifically, the control unit
200
includes a first NAND gate
201
with the clock input signal CLKin and the third shift signal s
3
as its inputs, a second NAND gate
202
with the clock input signal CLKin and the second shift signal s
2
as its inputs, and a third NAND gate
203
with the clock input signal CLKin and the first shift signal s
1
as its inputs.
The delay block
210
includes a fourth NAND gate
204
with the output of the first NAND gate
201
and a line input voltage Vcc as its inputs; a fifth NAND gate
205
with the output of the fourth NAND gate
204
and the line input voltage Vcc as its inputs; a sixth NAND gate
206
with the output of the second NAND gate
202
and the output of the fifth NAND gate
205
as its inputs; a seventh NAND gate
207
with the output of the sixth NAND gate
206
and the line input voltage Vcc as its inputs; an eighth NAND gate
208
with the output of the third NAND gate
203
and the output of the seventh NAND gate
207
as its inputs, and a ninth NAND gate
209
with the output of the eighth NAND gate
208
and the line input voltage Vcc as its inputs. The output unit
220
includes a tenth NAND gate having the output of the ninth NAND gate
209
and the line input voltage Vcc as its inputs.
For the sake of brevity, in the delay block
210
shown in
FIG. 2
, only three stages (termed unit delays) have been drawn, each having two NAND gates serially connected. In practice, however one hundred or more unit delays may be required. For example, the number of the unit delays required increases for lower frequency clock signals. Of course, including a large number of unit delays increases the chip size required for the DLL.
In operation, initially when the first shift signal s
1
is logic high, and the second and third shift signals s
2
and s
3
are logic low, the clock output signal CLKout is delayed from the clock input signal CLKin by one unit delay
230
. In this case, a time delay between the control unit
200
with the clock input signal CLKin as its input and the NAND gate
220
can be compensated by including it in delay monitor like the time delay of clock receiver, D-flip flop and output driver.
The clock output signal CLKout is relayed to the delay monitor
110
(FIG.
1
), which inputs a time-delayed signal to the phase detection unit
120
. As mentioned above, the phase detection unit
120
compares the time-delayed signal and the clock input signal CLKin. If it is necessary to further delay the clock output signal CLKout, the phase detection unit
120
activates the left shift signal. Thus, the first shift signal s
1
is rendered to logic low and the second shift signal s
2
is rendered to logic high. That is, the logic high signal is moved one unit delay to the left. Hereafter, the CLKout signal will be delayed two unit delays. If it is necessary to still further delay the clock output signal CLKout, the phase detection unit
120
activates the left shift signal, to thereby allow the third shift signal s
3
to be rendered logic high with the first and second shift signals being logic low. In this case, the clock output signal CLKout is delayed by three unit delays.
On the other hand, if the phase detection unit
120
determines that the delay of the clock output signal CLKout should be decreased, it activates the right shift signal to reduce the number of the unit delays used in delaying the clock input signal CLKin. The above procedure is repeatedly performed until the clock input signal CLKin and the clock output signal CLKout are synchronous in phase.
Since the number of the unit delays is proportional to a difference between one clock cycle, t
CK
, and a compensation delay, t
DM
, the number of unit delays increases as the clock frequency (i.e., the inverse of the clock cycle) gets lower. For example, when the unit delay is 0.1 nsec, and the t
CK
and the t
DM
are 15 nsec and 3 nsec, respectively,
120
unit delays are required.
As stated above, the conventional linear register-controlled DDL suffers from the disadvantage that since it employs a linear delay line, the number of unit delays required increases as clock frequency lowers, thereby resulting in large chip size. It is, therefore, desirable to provide a delay locked loop, for use in a semiconductor memory device, capable of operating in low frequency applications with a smaller chip size.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, a delay locked loop is provided for use in a semicond

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