Delay locked loop in semiconductor memory device and locking...

Details Delay locked loop in semiconductor memory device and locking... Delay locked loop in semiconductor memory device and locking...

2006-12-26

2006-12-26

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

07154311

ABSTRACT:
Provided is a delay locked loop (DLL) adapted for high-speed operation of a semiconductor memory device. The delay locked loop (DLL) includes: a clock buffer; a plurality of clock dividers; and a controller for activating an enable signal at a falling edge of a control clock by using a reset bar signal and a control clock outputted from the clock buffer.

REFERENCES:
patent: 6066968 (2000-05-01), Yang
patent: 6100736 (2000-08-01), Wu et al.
patent: 6621496 (2003-09-01), Ryan
patent: 05243975 (1993-09-01), None
patent: 2001-283589 (2001-10-01), None

Affiliated with

Also associated with

Rating

Delay locked loop in semiconductor memory device and locking... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay locked loop in semiconductor memory device and locking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop in semiconductor memory device and locking... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3654948