Delay locked loop having low jitter in semiconductor device

Details Delay locked loop having low jitter in semiconductor device Delay locked loop having low jitter in semiconductor device

2005-07-12

2005-07-12

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C375S376000

Reexamination Certificate

active

06917229

ABSTRACT:
A DLL circuit having a low jitter in a semiconductor device, includes a delay model unit for compensating a time difference between an external clock signal and an internal clock signals and generating a compensation signal; an input buffer for receiving a reference clock signal and an inverted clock signal, and for outputting a clock signal and an inverted clock signal activated at each edges of the reference clock signal and the inverted clock signal; a phase detection unit for generating a comparison signal by comparing the compensation signal with the inverted clock signal, and for outputting the comparison signal with a normal mode or a fast mode; a control unit for generating a plurality of control signals by receiving the comparison signal, the inverted clock signal and the clock signal; a delay unit for delaying in response to the plurality of control signals; and an output buffer for outputting a delayed clock signal by receiving an output signal of the duty corrector.

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