Delay locked loop having fast locking time

Details Delay locked loop having fast locking time Delay locked loop having fast locking time

2000-12-19

2002-01-29

Phan, Trong (Department: 2818)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S155000, C327S161000

Reexamination Certificate

active

06342796

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop having a fast locking time.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed operation in a semiconductor memory device, a synchronous dynamic access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Generally, when data are outputted in synchronization with the external clock, a skew between the external clock signal and the output data is occurred. In the SDRAM, a delay locked loop (DLL) can be used to compensate for the skew between an external clock and an output data, or an external clock and an internal clock.
FIG. 1
is a block diagram showing a conventional delay locked loop.
Referring to
FIG. 1
, the conventional delay locked loop includes a clock buffer
100
, a clock divider
110
, a phase comparator
120
, a shift controller
130
, a shift register
140
, a delay line unit
150
, a delay model
160
and a DLL signal driver
170
.
The clock buffer
100
generates a rising clock RCLK and a falling clock FCLK in response to a rising edge and a falling edge of an external clock CLK, respectively.
The clock divider
110
generates a first pulse signal DELAY_IN and a second pulse signal REF. The first pulse signal DELAY_IN is generated at every 8 external clocks in response to the rising clock RCLK and has a pulse width corresponding to one period of the external clock CLK. The second pulse signal REF is obtained by inverting the first pulse signal DELAY_IN.
The phase comparator
120
compares a phase of the second pulse signal REF with that of a feedback signal FEEDBACK outputted from the delay model
160
to thereby output a comparison signal PC<
0
:
3
>.
In response to the comparison signal PC<
0
:
3
>, the shift controller
130
generates a shift-right signal SR and a shift-left signal SL for determining a shift direction. The shift register
140
performs a shift-right operation and a shift-left operation in response to the shift-right signal SR and the shift-left signal SL, respectively.
The delay line unit
150
includes a first to a third delay lines
151
to
153
for controlling each delay amount of the falling clock FCLK, the rising clock RCLK and the first pulse signal DELAY_IN, respectively. The first to third delay lines
151
to
153
generate a first to a third delayed signals FCLK_DLL, RCLK_DLL and FEEDBACK_DLY, respectively. The delay line unit
150
is implemented a plurality of unit delay circuits.
The delay model
160
compensates a skew between the external clock CLK and the internal clocks according to the third delayed signal FEEDBACK_DLY. An output of the delay model
160
is fed back to the phase comparator
120
. The DLL signal driver
170
drives the first and the second delayed signals FCLK_DLL and RCLK_DLL signal.
At this time, in case where pulse widths of the second pulse signal REF, the unit delay circuit and the delay model are respectively 5 nsec, 0.2 nsec and 5 nsec, a pulse width of the feedback signal FEEDBACK becomes 5.2 nsec. Thus, the feedback signal FEEDBACK is generated later than the second pulse signal REF. In this case, the phase comparator
120
must generates a shift-left signal SL from the beginning. However, the delay line unit
150
cannot perform a shift-left operation from the beginning, so that it is impossible to obtain desired internal clocks.
Additionally, since the unit delay circuit contained in the delay line unit
150
has a small unit delay of about 0.2 nsec, it takes a long time to compare a phase of the second pulse signal REF with that of the feedback signal FEEDBACK in order to obtain a locking.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a delay locked loop having a fast locking time.
In accordance with an aspect of the present invention, there is provided a delay locked loop (DLL) for use in a synchronous memory device, comprising: a first shift control means for generating a first shift-right signal in response to a first comparison signal; a first shift register for performing only a shift-right operation in response to the first shift-right signal; a first delay line means for controlling each delay amount of internal signals in response to an output of the first shift register, wherein the first delay line means includes a plurality of delay lines, each delay line having a first unit delay; a second shift control means for generating a second shift-right signal and a shift-left signal in response to a second comparison signal; a second shift register for performing a shift-right operation and a shift-left operation in response to the second shift-right signal and the shift-left signal, respectively; and a second delay line means for controlling each delay amount of output signals of the first delay line means, wherein the second delay line means includes a plurality of delay lines, each delay line having a second unit delay smaller than the first unit delay.


REFERENCES:
patent: 5815016 (1998-09-01), Erickson
patent: 6064244 (2000-05-01), Wakayama et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6100736 (2000-08-01), Wu et al.
patent: 6208183 (2001-03-01), Li et al.
patent: 6229363 (2001-05-01), Eto et al.

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