Delay-locked loop having a plurality of lock modes

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S158000

Reexamination Certificate

active

11286454

ABSTRACT:
A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.

REFERENCES:
patent: 6337590 (2002-01-01), Millar
patent: 6496048 (2002-12-01), Sikkink
patent: 6670835 (2003-12-01), Yoo
patent: 2003/0199262 (2003-10-01), Chung
patent: 2004/0125905 (2004-07-01), Vlasenko et al.
U.S. Appl. No. 11/327,572, filed Jan. 6, 2006, entitled: “Delay Line Periodically Operated in a Closed Loop,” naming inventor Anand Daga.
U.S. Appl. No. 11/240,231, filed Sep. 30, 2005, entitled: “Voltage Controlled Delay Line (VCDL) Having Embedded Multiplexer and Interpolation Functions,” naming inventors Rohit Kumar and Anand Daga.
Garlepp, Bruno W., et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 632-644.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Sidiropoulos, Stafanos and Horowitz, Mark A., “A Semidigital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.

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