Delay locked loop having a mis-lock detecting circuit

Details Delay locked loop having a mis-lock detecting circuit Delay locked loop having a mis-lock detecting circuit

1999-06-15

2001-07-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S269000

Reexamination Certificate

active

06259290

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a delay locked loop for use in N-multiplication circuits, multi-phase clock generators or the like, which delays an input signal by the time corresponding to a control voltage. The invention also relates to a delay locked loop that has a mis-lock detecting circuit and generating a control signal to release the loop from a mis-locked state.
FIG. 1
shows an N-multiplication circuit having a conventional delay locked loop.
The N-multiplication circuit comprises a DLL (Delay Locked Loop)
101
and an N-multiplied signal synthesizing circuit
102
. The DLL
101
comprises a voltage-controlled delay section
103
, a phase comparator (PHC)
104
, a low-pass filter (LPF)
105
, and a mis-lock detector
106
.
The voltage-controlled delay circuit
103
comprises a plurality of voltage-controlled delay circuits that are connected in series. A reference signal FREF is input to the voltage-controlled delay section
103
. The voltage-controlled delay circuits operate sequentially, each delaying the reference signal FREF delayed by the immediately preceding voltage-controlled delay circuit. The delay time of each voltage-controlled delay circuit is controlled by the voltage of a control signal LPFO output from the low-pass filter
105
.
The phase comparator
104
has two input terminals. One input terminal receives the reference signal FREF. The other input terminal receives the delayed signal FSIG supplied from the last delay circuit of the voltage-controlled delay section
103
. The phase comparator
104
detects the phase difference between the two input signals, at the leading edges of the input signals or the trailing edges thereof. The comparator
104
outputs an error signal VERR representing the phase difference it has detected. The phase comparator
104
also receives an up-signal output from the mis-lock detector
106
, as will be described later. In the comparator
104
, the error signal VERR is set at high level in accordance with the logic value of the up-signal. The error signal VERR is input to the low-pass filter
105
.
The low-pass filter
105
extracts the direct-current component from the error signal VERR and supplies the component, as a control signal, to the voltage-controlled delay section
103
.
The delayed signals S
1
to S
4
output from the voltage-controlled delay circuits of the section
103
are input to the mis-lock detecting circuit
106
. More specifically, the delayed signals S
1
and S
2
output by the two voltage-controlled delay circuits, which are different in phase from the reference signal FREF, are inverted by two inverters, respectively, and input to the AND circuit
107
provided in the mis-lock detecting circuit
106
. And the delayed signals S
3
and S
4
output by the two other voltage-controlled delay circuits, which are more different in phase from the reference signal FREF than the signals S
1
and S
2
, are input to the AND circuit
107
without being inverted. The output of the AND circuit
107
is input to the latch circuit
108
incorporated in the mis-lock detecting circuit
106
. The output of the latch circuit
108
is input, as up-signal, to the phase comparator
104
. The latch circuit
108
receives the reference signal FREF at its clock input terminal.
The N-multiplied signal synthesizing circuit
102
receives n number of multi-phase clock signals F
1
to Fn which have been output from the voltage-controlled delay section
103
and which differ in phase from one another. Using these multi-phase clock signals F
1
to Fn, the signal synthesizing circuit
102
generates an N-multiplied signal.
In the DLL
101
, the voltage-controlled delay section
103
, the phase comparator
104
and low-pass filter
105
constitute a closed loop circuit. The closed loop circuit controls the voltage of the control signal LPFO so that the phase difference between the reference signal FREF and the delayed signal FSIG output by the delay section
103
may be substantially eliminated.
As long as the DLL
101
remains normally locked, the delayed signal FSIG output from the voltage-controlled delay section
103
is delayed by one cycle with respect to the reference signal FREF. The phases of the delayed signal FSIG and reference signal FREF are compared by the phase comparator
104
, at the leading edge or the trailing edge only. In the conventional delay locked loop (FIG.
1
), it is therefore impossible to detect whether or not the components of the voltage-controlled delay section
103
are operating normally at all.
FIG. 2
illustrates the internal state of the voltage-controlled delay section
103
and the relationship of the four delayed signals S
1
to S
4
.
The voltage-controlled delay section
103
assumes State 1 when all components operate normally. While remaining in State 1, the circuit
103
generates a signal that is delayed by one cycle with respect to the reference signal FREF. As long as the circuit
103
stays in State 1, the delayed signals S
1
and S
2
remain at low level, and the delayed signals S
3
and S
4
remain at high level. At the leading edge of the reference signal FREF, the latch circuit
108
latches the output signal of the AND circuit
107
. The up-signal is thereby set at high level. In this case, it is determined that the DLL
101
is normally locked, and the output signal of the phase comparator
104
is not forcibly set into up-state, or set at high level. Thus, the DLL
101
keeps operating normally.
The voltage-controlled delay section
103
may delay the reference signal FREF twice as much as it delays the signal FREF while the DLL
101
is normally locked. If so, the circuit
103
assumes State 2 (i.e., 1/2-locked state). In this case, the delayed signal S
2
is at low level, though it should be at high level, and the delayed signal S
3
is at high level, though it should be at low level. While the voltage-controlled delay section
103
remains in State 2, the output signal of the AND circuit
107
of the mis-lock detecting circuit
106
remains at low level. Hence, the up-signal, i.e., the output signal of the latch circuit
108
latching the output signal of the AND circuit
107
, also remains at low level. As a result, it is determined that the DLL
101
is mis-locked. The output signal of the phase comparator
104
is forcibly set at high level. The voltage-controlled delay section
103
is thereby controlled, shortening the delay time of each voltage-controlled delay circuit incorporated in the circuit
103
.
The voltage-controlled delay section
103
may delay the reference signal FREF by a delay time, which corresponds to three cycles of the reference signal FREF. If so, the circuit
103
assumes State 3 (i.e., 1/3-locked state). In this case, the delayed signals S
1
and S
2
are at low level and the delayed signals S
3
and S
4
are at high level, as in the case where the circuit
103
assumes State 1. Hence, the mis-lock detecting circuit
106
determines as if the DLL
101
were normally locked.
To prevent such erroneous determination, the voltage-controlled delay section
103
may have more voltage-controlled delay circuits so that the mis-lock detecting circuit
106
may detect more delayed signals and the phases thereof. Even if this measure is taken, erroneous determination will occur when the reference signal FREF is delayed much more.
The voltage-controlled delay section
103
assumes State 4 when the mis-lock detecting circuit
106
determines can correctly determine that the DLL
101
is erroneously locked.
Thus, it is impossible to detect that the DLL is erroneously locked, when the voltage-controlled delay section
103
assumes a particular internal sate.
In the conventional DLL
101
, the delayed signals S
1
to S
4
input to the AND circuit
107
are predetermined. The reference signal FREF input to the voltage-controlled delay section
103
therefore needs to have a fixed duty. In other words, all signals having different duties cannot be used as reference signal FREF in the conventional DLL
101
.
The conventional DLL
101

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