Delay locked loop for use in semiconductor memory device and...

Details Delay locked loop for use in semiconductor memory device and... Delay locked loop for use in semiconductor memory device and...

2008-05-06

2008-05-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000, C327S163000, C331S025000, C365S233100

Reexamination Certificate

active

07368963

ABSTRACT:
A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locked clock signal by a predetermined number determined based on a column address strobe (CAS) latency to thereby generate a divided signal; and a delay line control unit for generating the delay amount control signal based on a result of comparing a phase of the external clock signal and a delayed signal of the divided signal.

REFERENCES:
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 6094080 (2000-07-01), Jeong et al.
patent: 6100736 (2000-08-01), Wu et al.
patent: 7027352 (2006-04-01), Jung
patent: 7046042 (2006-05-01), Dino et al.
patent: 10-0224718 (1999-07-01), None
patent: 2003-0078129 (2003-10-01), None

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